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参数资料
型号： ATMEGA103-6AI
厂商： Atmel
文件页数： 130/141页
文件大小： 0K
描述： IC MCU 128K 6MHZ A/D IT 64TQFP
产品培训模块： megaAVR Introduction
标准包装： 90
系列： AVR® ATmega
核心处理器： AVR
芯体尺寸： 8-位
速度： 6MHz
连通性： SPI，UART/USART
外围设备： POR，PWM，WDT
输入/输出数： 32
程序存储器容量： 128KB（64K x 16）
程序存储器类型： 闪存
EEPROM 大小： 4K x 8
RAM 容量： 4K x 8
电压 - 电源 (Vcc/Vdd)： 4 V ~ 5.5 V
数据转换器： A/D 8x10b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 64-TQFP
包装： 托盘
配用： ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
89
ATmega103(L)
0945I–AVR–02/07
Note:
n: 7,6...0, pin number
Alternate Functions of Port B
The alternate pin configuration is as follows:
OC2/PWM2, Bit 7
OC2/PWM2, Output Compare output for Timer/Counter2 or PWM output when
Timer/Counter2 is in PWM mode. The pin has to be configured as an output to serve
this function.
OC1B/PWM1B, Bit 6
OC1B/PWM1B, Output Compare output B for Timer/Counter1 or PWM output B when
Timer/Counter1 is in PWM mode. The pin has to be configured as an output to serve
this function.
OC1A/PWM1A, Bit 5
OC1A/PWM1A, Output Compare output A for Timer/Counter1 or PWM output A when
Timer/Counter1 is in PWM mode. The pin has to be configured as an output to serve
this function.
OC0/PWM0, Bit 4
OC0/PWM0, Output Compare output for Timer/Counter0 or PWM output when
Timer/Counter0 is in PWM mode. The pin has to be configured as an output to serve
this function.
MISO – Port B, Bit 3
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is
enabled as a Master, this pin is configured as an input regardless of the setting of
DDB3. When the SPI is enabled as a Slave, the data direction of this pin is controlled by
DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB3 bit. See the description of the SPI port for further details.
MOSI – Port B, Bit 2
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB2.
When the SPI is enabled as a Master, the data direction of this pin is controlled by
DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB2 bit. See the description of the SPI port for further details.
SCK – Port B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB1.
When the SPI is enabled as a Master, the data direction of this pin is controlled by
Table 30. DDBn Effects on Port B Pins
DDBn
PORTBn
I/O
Pull-up
Comment
0
Input
No
Tri-state (high-Z)
0
1
Input
Yes
PBn will source current if ext. pulled low
1
0
Output
No
Push-pull Zero Output
1
Output
No
Push-pull One Output
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