参数资料
型号: ATMEGA103-6AI
厂商: Atmel
文件页数: 55/141页
文件大小: 0K
描述: IC MCU 128K 6MHZ A/D IT 64TQFP
产品培训模块: megaAVR Introduction
标准包装: 90
系列: AVR® ATmega
核心处理器: AVR
芯体尺寸: 8-位
速度: 6MHz
连通性: SPI,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 128KB(64K x 16)
程序存储器类型: 闪存
EEPROM 大小: 4K x 8
RAM 容量: 4K x 8
电压 - 电源 (Vcc/Vdd): 4 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 托盘
配用: ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
20
ATmega103(L)
0945I–AVR–02/07
Note:
Reserved and unused locations are not shown in the table.
All the different ATmega103(L) I/Os and peripherals are placed in the I/O space. The dif-
ferent I/O locations are directly accessed by the IN and OUT instructions transferring
data between the 32 general purpose working registers and the I/O space. I/O Registers
within the address range $00 - $1F are directly bit-accessible using the SBI and CBI
instructions. In these registers, the value of single bits can be checked by using the
SBIS and SBIC instructions. Refer to the “Instruction Set Summary” on page 135 for
more details. When using the I/O specific instructions IN and OUT, the I/O Register
address $00 - $3F are used. When addressing I/O Registers as SRAM, $20 must be
added to this address. All I/O Register addresses throughout this document are shown
with the SRAM address in parentheses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical “1” to them. Note that the CBI
and SBI instructions will operate on all bits in the I/O Register, writing a one back into
any flag read as set, thus clearing the flag. The CBI and SBI instructions work with reg-
isters $00 to $1F only.
The different I/O and peripherals control registers are explained in the following
sections.
Status Register – SREG
The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:
Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
Global Interrupt Enable Register is cleared (zero), none of the interrupts are enabled
independent of the individual interrupt enable settings. The I-bit is cleared by hardware
after an interrupt has occurred and is set by the RETI instruction to enable subsequent
interrupts.
Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the Register File can be cop-
$06 ($26)
ADCSR
ADC Control and Status Register
$05 ($25)
ADCH
ADC Data Register High
$04 ($24)
ADCL
ADC Data Register Low
$03 ($23)
PORTE
Data Register, Port E
$02 ($22)
DDRE
Data Direction Register, Port E
$01 ($21)
PINE
Input Pins, Port E
$00 ($20)
PINF
Input Pins, Port F
Table 2. ATmega103(L) I/O Space (Continued)
I/O Address (SRAM
Address)
Name
Function
Bit
765
432
1
0
$3F ($5F)
I
T
H
S
V
N
Z
C
SREG
Read/Write
R/W
Initial Value
0
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