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参数资料
型号： ATMEGA103-6AI
厂商： Atmel
文件页数： 57/141页
文件大小： 0K
描述： IC MCU 128K 6MHZ A/D IT 64TQFP
产品培训模块： megaAVR Introduction
标准包装： 90
系列： AVR® ATmega
核心处理器： AVR
芯体尺寸： 8-位
速度： 6MHz
连通性： SPI，UART/USART
外围设备： POR，PWM，WDT
输入/输出数： 32
程序存储器容量： 128KB（64K x 16）
程序存储器类型： 闪存
EEPROM 大小： 4K x 8
RAM 容量： 4K x 8
电压 - 电源 (Vcc/Vdd)： 4 V ~ 5.5 V
数据转换器： A/D 8x10b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 64-TQFP
包装： 托盘
配用： ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
22
ATmega103(L)
0945I–AVR–02/07
instruction and it is incremented by 2 when an address is popped from the Stack with
return from subroutine RET or return from interrupt RETI.
RAM Page Z Select Register –
RAMPZ
The RAMPZ Register is normally used to select which 64K RAM page is accessed by
the Z pointer. As the ATmega103(L) does not support more than 64K of SRAM memory,
this register is used only to select which page in the Program memory is accessed when
the ELPM instruction is used. The different settings of the RAMPZ0 bit have the follow-
ing effects:
Note that LPM is not affected by the RAMPZ setting.
MCU Control Register –
MCUCR
The MCU Control Register contains control bits for general MCU functions.
Bit 7 – SRE: External SRAM Enable
When the SRE bit is set (one), the external Data SRAM is enabled, and the pin functions
AD0 - 7 (Port A), and A8 - 15 (Port C) are activated as the alternate pin functions. Then
the SRE bit overrides any pin direction settings in the respective Data Direction Regis-
ters. When the SRE bit is cleared (zero), the external Data SRAM is disabled and the
normal pin and data direction settings are used.
Bit 6 – SRW: External SRAM Wait State
When the SRW bit is set (one), a one-cycle wait state is inserted in the external Data
SRAM access cycle. When the SRW bit is cleared (zero), the external Data SRAM
access is executed with a three-cycle scheme. See Figure 51 on page 85 and Figure 52
on page 85.
Bit 5 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the pro-
grammer’s purpose, it is recommended to set the Sleep Enable (SE) bit just before the
execution of the SLEEP instruction.
Bit
765
432
1
0
$3B ($5B)
–––
–
RAMPZ0
RAMPZ
Read/Write
RR
RRR
RR
R/W
Initial Value
0
RAMPZ0 = 0:
Program memory address $0000 - $7FFF (lower 64K bytes) is
accessed by ELPM
RAMPZ0 = 1:
Program memory address $8000 - $FFFF (higher 64K bytes) is
accessed by ELPM
Bit
7
6
543
21
0
$35 ($55)
SRE
SRW
SE
SM1
SM0
–
MCUCR
Read/Write
R/W
R
Initial Value
0
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