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参数资料
| 型号： | CLRC63201T |
| 厂商： | NXP Semiconductors N.V. |
| 元件分类： | 通信及网络 |
| 英文描述： | Multiple protocol contactless reader IC (MIFARE-I-CODE1) |
| 封装： | CLRC63201T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 5, 2005,; |
| 文件页数： | 49/126页 |
| 文件大小： | 719K |
| 代理商： | CLRC63201T |
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CLRC632_35
NXP B.V. 2009. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.5 — 10 November 2009
073935
29 of 126
NXP Semiconductors
CLRC632
Multiple protocol contactless reader IC (MIFARE/I-CODE1)
9.6.3 Standby mode
The Standby mode is immediately entered when the Control register StandBy bit is set. All
internal current sinks, including the internal digital clock buffer are switched off. However,
the oscillator buffer is not switched off.
The digital input buffers are not separated by the input pads, keeping their functionality
and the digital output pins do not change their state. In addition, the oscillator does not
need time to wake-up.
After resetting the Control register StandBy bit, it takes four clock cycles on pin OSCIN for
Standby mode to exit. Resetting bit StandBy does not immediately clear it. It is
automatically cleared when the Standby mode is exited.
9.6.4 Automatic receiver power-down
It is a power saving feature to switch off the receiver circuit when it is not needed. Setting
bit RxAutoPD = logic 1, automatically powers down the receiver when it is not in use.
Setting bit RxAutoPD = logic 0, keeps the receiver continuously powered up.
9.7 StartUp phase
The events executed during the StartUp phase are shown in Figure 10.
9.7.1 Hard power-down phase
The hard power-down phase is active during the following cases:
a Power-On Reset (POR) caused by power-up on pins DVDD or AVDD activated
when VDDD or VDDA is below the digital reset threshold.
a HIGH-level on pin RSTPD which is active while pin RSTPD is HIGH. The HIGH level
period on pin RSTPD must be at least 100
s (tPD ≥ 100 s). Shorter phases will not
necessarily result in the reset phase (treset). The rising or falling edge slew rate on pin
RSTPD is not critical because pin RSTPD is a Schmitt trigger input.
9.7.2 Reset phase
The reset phase automatically follows the Hard power-down. Once the oscillator is
running stably, the reset phase takes 512 clock cycles. During the reset phase, some
register bits are preset by hardware. The respective reset values are given in the
description of each register (see Section 10.5 on page 50).
Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to
become stable. This is because the internal oscillator is supplied by VDDA and any clock
cycles will not be detected by the internal logic until VDDA is stable.
Fig 10. The StartUp procedure
001aak613
StartUp phase
states
tRSTPD
treset
tinit
Hard power-
down phase
Reset phase
Initialising
phase
ready
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CLRC63201T/0FE | 制造商:NXP Semiconductors 功能描述: |
| CLRC63201T/0FE,112 | 功能描述:RFID应答器 I.CODE HS READER RoHS:否 制造商:Murata 存储容量:512 bit 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| CLRC63201T/0FE,118 | 制造商:NXP Semiconductors 功能描述:Interface Misc |
| CLRC63201T/0FE112 | 制造商:NXP Semiconductors 功能描述:CNTCLESS RC 5V ISO14443 + ISO15693 |
| CLRC663 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Contactless reader IC |
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