
CLRC632_35
NXP B.V. 2009. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.5 — 10 November 2009
073935
68 of 126
NXP Semiconductors
CLRC632
Multiple protocol contactless reader IC (MIFARE/I-CODE1)
10.5.5 Page 4: RF Timing and channel redundancy
10.5.5.1
Page register
10.5.5.2
RxWait register
Selects the time interval after transmission, before the receiver starts.
10.5.5.3
ChannelRedundancy register
Selects kind and mode of checking the data integrity on the RF channel.
Table 99.
RxWait register (address: 21h) reset value: 0000 0101b, 06h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
RxWait[7:0]
Access
R/W
Table 100. RxWait register bit descriptions
Bit
Symbol
Function
7 to 0
RxWait[7:0]
after data transmission, the activation of the receiver is delayed
for RxWait bit-clock cycles. During this frame guard time any
signal on pin RX is ignored.
Table 101. ChannelRedundancy register (address: 22h) reset value: 0000 0011b, 03h bit
allocation
Bit
7
6
5
4
3
2
1
0
Symbol
00
CRC3309
CRC8
RxCRCEn TxCRCEn ParityOdd
ParityEn
Access
R/W
Table 102. ChannelRedundancy bit descriptions
Bit
Symbol
Value
Function
7 to 6 00
-
this value must not be changed
5
CRC3309
1
CRC calculation is performed using ISO/IEC 3309
(ISO/IEC 14443 B) and ISO/IEC 15693
0
CRC calculation is performed using ISO/IEC 14443 A and I-CODE1
4
CRC8
1
an 8-bit CRC is calculated
0
a 16-bit CRC is calculated
3
RxCRCEn
1
the last byte(s) of a received frame are interpreted as CRC bytes. If
the CRC is correct, the CRC bytes are not passed to the FIFO. If
the CRC bytes are incorrect, the CRCErr ag is set.
0
no CRC is expected
2
TxCRCEn
1
a CRC is calculated over the transmitted data and the CRC bytes
are appended to the data stream
0
no CRC is transmitted