
CLRC632_35
NXP B.V. 2009. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.5 — 10 November 2009
073935
56 of 126
NXP Semiconductors
CLRC632
Multiple protocol contactless reader IC (MIFARE/I-CODE1)
[1]
Only valid for communication using ISO/IEC 14443 A.
10.5.2.4
CollPos register
Bit position of the rst bit-collision detected on the RF interface.
Remark: A bit collision is not indicated in the CollPos register when using the
ISO/IEC 14443 B protocol standard.
5
AccessErr
1
set when the access rights to the EEPROM are violated
0
set when an EEPROM related command starts
4
FIFOOv
1
set when the microprocessor or CLRC632 internal state machine
(e.g. receiver) tries to write data to the FIFO buffer when it is full
3
CRCErr
1
set when RxCRCEn is set and the CRC fails
0
automatically set during the PrepareRx state in the receiver start
phase
2
FramingErr
1
set when the SOF is incorrect
0
automatically set during the PrepareRx state in the receiver start
phase
1
ParityErr
1
set when the parity check fails
0
automatically set during the PrepareRx state in the receiver start
phase
0
CollErr
1
set when a bit-collision is detected
[1]0
automatically set during the PrepareRx state in the receiver start
Table 60.
ErrorFlag register bit descriptions …continued
Bit
Symbol
Value
Description
Table 61.
CollPos register (address: 0Bh) reset value: 0000 0000b, 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
CollPos[7:0]
Access
R
Table 62.
CollPos register bit descriptions
Bit
Symbol
Description
7 to 0
CollPos[7:0]
this register shows the bit position of the rst detected collision in a
received frame.
Example:
00h indicates a bit collision in the start bit
01h indicates a bit collision in the 1st bit
...
08h indicates a bit collision in the 8th bit