参数资料
| 型号： | CORE8051-AR |
| 厂商： | Microsemi SoC |
| 文件页数： | 20/41页 |
| 文件大小： | 0K |
| 描述： | IP MODULE CORE8051 |
| 标准包装： | 1 |
| 系列： | * |
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Core8051
Table 17 ? PSW Flag Modification (CY, OV, AC) (Continued)
Flag
Flag
Instruction
DIV
DA
RRC
RLC
CY
0
X
X
X
OV
X
–
–
–
AC
–
–
–
–
Instruction
ANL C,~bit
ORL C,bit
ORL C,~bit
MOV C,bit
CY
X
X
X
X
OV
–
–
–
–
AC
–
–
–
–
CJNE
X
–
–
Note: In this table, 'X' denotes that the indicated flag is affected by the instruction and can be a logic 1 or logic 0, depending upon
specific calculations. If a particular box is blank, that flag is unaffected by the listed instruction.
Instruction Timing
Program Memory Bus Cycle
The execution for instruction N is performed during the
fetch of instruction N+1. A program memory fetch cycle
without wait states is shown in Figure 4 . A program
states is shown in Figure 6 on page 21 . A program
The following conventions are used in Figure 4 to
Convention
Tclk
N
(N)
N+1
Addr
Data
read sample
write sample
ramcs
20
Description
Time period of clk signal
Address of actually executed instruction
Instruction fetched from address N
Address of next instruction
Address of memory cell
Data read from address Addrl
Point of reading the data from the bus into the internal register
Point of writing the data from the bus into memory
Off-core signal is made on the base ramwe and clk signals
v6.0
相关PDF资料 |
PDF描述 |
|---|---|
| COREFFT-RM | IP MODULE COREFFT |
| COREFIR-RM | IP MODULE COREFIR |
| COREPCIF-RM | IP MODULE COREPCIF |
| COREU1LL-AR | IP MODULE COREU1LL |
| COREU1PHY-AR | IP MODULE COREU1PHY |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CORE8051-EV | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-SN | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-SR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-UR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-XX | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
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