参数资料
型号: CORE8051-AR
厂商: Microsemi SoC
文件页数: 27/41页
文件大小: 0K
描述: IP MODULE CORE8051
标准包装: 1
系列: *
Core8051
External Special Function Register Bus Cycle
Example bus cycles for external SFR access are shown in Figure 18 and Figure 19 . Figure 18 shows an external SFR read
cycle. Figure 19 shows an external SFR write cycle.
0ns
50ns
100ns
150ns
200ns
250ns
300ns
clk
sfraddr
sfroe
sfrwe
sfrdatao
Addr
Addr
sfrdatai
max 1*Tclk
Data
max 1*Tclk
read sample
max 1*Tclk
Data
max 1*Tclk
read sample
Figure 18 ? External SFR Read Cycle
0ns
50ns
100ns
150ns
200ns
250ns
250ns
clk
sfraddr
sfroe
sfrwe
sfrdatao
sfrdatai
Figure 19 ? External SFR Write Cycle
Addr
Data
write sample
Addr
Data
write
sample
Core8051 Engine
The main engine of Core8051 is composed of four
components:
? Control Unit
B Register (b)
The b register is used during multiply and divide
instructions. It can also be used as a scratch-pad register
to hold temporary data.
?
?
Arithmetic Logic Unit
Memory Control Unit
Program Status Word (psw)
? RAM and SFR Control Unit
The Core8051 engine controls instruction fetches from
program memory and execution using RAM or SFR. This
The psw register flags and bit functions are listed in
Table 19 ? psw Register Flags
section describes the main engine registers.
cy
ac
f0
rs1
rs
ov
p
Accumulator (acc)
The acc register is the accumulator. Most instructions use
the accumulator to hold the operand. The mnemonics
for accumulator-specific instructions refer to the
accumulator as A, not ACC.
v6.0
27
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