参数资料
| 型号： | CORE8051-AR |
| 厂商： | Microsemi SoC |
| 文件页数： | 6/41页 |
| 文件大小： | 0K |
| 描述： | IP MODULE CORE8051 |
| 标准包装： | 1 |
| 系列： | * |
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Core8051
Table 5 ? Core8051 Pin Description
Name
Type
Polarity/Bus Size Description
port0i
port0o
port1i
port1o
port2i
port2o
port3i
port3o
clk
clkcpu
Input
Output
Input
Output
Input
Output
Input
Output
Input
Input
8
8
8
8
8
8
8
8
Rise
Rise
Port 0
8-bit bidirectional I/O port with separated inputs and outputs
Port 1
8-bit bidirectional I/O port with separated inputs and outputs
Port 2
8-bit bidirectional I/O port with separated inputs and outputs
Port 3
8-bit bidirectional I/O port with separated inputs and outputs
Clock input for internal logic
CPU Clock input for internal controller logic (must either be the same as the clk
input or a gated version of the clk input)
clkper
Input
Rise
Peripheral Clock input for internal peripheral logic (must either be the same as
the clk input or a gated version of the clk input)
clkcpu_en
Output
High
CPU Clock Enable
This output may be used to optionally create a gated version of the clk input
signal for connection to the clkcpu input (see "Power Management
clkper_en
Output
High
Peripheral Clock Enable
This output may be used to optionally create a gated version of the clk input
signal for connection to the clkper input (see "Power Management
nreset
Input
Low
Hardware Reset Input
A logic 0 on this pin for two clock cycles while the oscillator is running resets the
device.
nrsto
Output
Low
Peripheral Reset Output
This globally buffered signal can be connected to logic outside Core8051 to
provide an active-low asynchronous reset to peripherals.
nrsto_nc
Bidirectional
(no-connect)
Low
Peripheral Reset No-Connect
This signal is connected to nrsto internally and is only used by the SX-A/RTSX-S
implementations, in which case it must be brought up to a top-level package pin
and left unconnected at the board-level. This signal should not be used
(connected) for any other device families.
movx
Output
High
Movx instruction executing
On-Chip Debug Interface (Optional)
TCK
TMS
TDI
TDO
nTRST
dbgmempswr
6
Input
Input
Input
Output
Input
Output
Rise
High
High
High
Low
High
JTAG test clock. If OCI is not used, connect to logic 1.
JTAG test mode select. If OCI is not used, connect to logic 0.
JTAG test data in. If OCI is not used, connect to logic 0.
JTAG test data out
JTAG test reset. If OCI is not used, connect to logic 1.
Optional debug program storage write
v6.0
相关PDF资料 |
PDF描述 |
|---|---|
| COREFFT-RM | IP MODULE COREFFT |
| COREFIR-RM | IP MODULE COREFIR |
| COREPCIF-RM | IP MODULE COREPCIF |
| COREU1LL-AR | IP MODULE COREU1LL |
| COREU1PHY-AR | IP MODULE COREU1PHY |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CORE8051-EV | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-SN | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-SR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-UR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-XX | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
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