参数资料
型号: CORE8051-AR
厂商: Microsemi SoC
文件页数: 33/41页
文件大小: 0K
描述: IP MODULE CORE8051
标准包装: 1
系列: *
Core8051
Priority Level Structure
All interrupt sources are combined in priority level
groups and controlled in terms of priority level by bits in
the ip0 and ip1 registers.
Table 35 displays the Interrupt Priority 0 register (ip0).
Table 35 ? ip0 Register
Table 39 displays the polling sequence.
Table 39 ? Polling Sequence
External interrupt 0(ie0)
int0a
int1a
MSB
LSB
Timer 0 interrupt
ip0.5
ip0.4
ip0.3
ip0.2
ip0.1
ip0.0
int2
External interrupt 1(ie1)
Table 36 displays the Interrupt Priority 1 register (ip1).
Table 36 ? ip1 Register
int3
Timer 1 interrupt
MSB
LSB
int4
ip1.5
ip1.4
ip1.3
ip1.2
ip1.1
ip1.0
Serial channel 0 interrupt
Each group of interrupt sources can be programmed
individually to one of four priority levels by setting or
clearing one bit in the special function register ip0 and
one in ip1. If requests of the same priority level are
received simultaneously, an internal polling sequence
determines which request is serviced first.
For example, in Table 38 the two interrupts, Timer 0
interrupt and external pin int2, are combined in a
priority group and are priority level controlled by the
combination of bit0 from the ip0 register and bit0 from
int5
int6
int7
Interrupt Vectors
The interrupt vector addresses are listed in Table 40 .
Table 40 ? Interrupt Vector Addresses
the ip1 register.
Table 37 displays the priority levels.
Table 37 ? Priority Levels
Interrupt Request Flags
ie0 – External interrupt 0
Interrupt Vector
Address
0003H
ip1.x
0
0
1
1
ip0.x
0
1
0
1
Priority Level
Level0 (lowest)
Level1
Level2
Level3 (highest)
tf0 – Timer 0 interrupt
ie1 – External interrupt 1
tf1 – Timer 1 interrupt
ri0/ti0 – Serial channel 0 interrupt
int6
000BH
0013H
001BH
0023H
002BH
Table 38 displays the groups of priority.
Table 38 ? Groups of Priority
int0a
int1a
0083H
0043H
Bit
ip1.0,ip0.0
ip1.1,ip0.1
ip1.2,ip0.2
ip1.3,ip0.3
ip1.4,ip0.4
ip1.5,ip0.5
Group
External interrupt 0(ie0), int0a, int1a
Timer 0 interrupt, int2
External interrupt 1(ie1), int3
Timer 1 interrupt, int4
Serial channel 0 interrupt, int5
int6, int7
v6.0
int2
int3
int4
int5
int7
004BH
0053H
005BH
0063H
006BH
33
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