参数资料
| 型号： | CORE8051-AR |
| 厂商： | Microsemi SoC |
| 文件页数： | 39/41页 |
| 文件大小： | 0K |
| 描述： | IP MODULE CORE8051 |
| 标准包装： | 1 |
| 系列： | * |
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Core8051
Debugger Program
The debugger can submit an instruction to the CPU. The
OCI logic uses a multiplexer on the program memory
input bus (memdatai) to optionally override the user
instruction with the debugger instruction.
The interrupts are disabled during execution of the
debugger program. Setting the interrupt flag does not
cause an interrupt request.
The power down IDLE and STOP modes are supported.
The CPU can only exit the IDLE or STOP state with a reset.
Hardware Breakpoint
The debugger can monitor the program memory address
bus (memaddr) for optional hardware breakpoint
addresses. When a fetch is noted from this address, the
debugger can replace the original user instruction with
opcode 0xA5.
When the CPU executes the opcode 0xA5, the core enters
the debug mode and asserts the debugack signal. The
debugger responds by setting debugreq high.
Program Trace
Core8051 provides several signals for tracing program
execution. Two signals, fetch and flush, are internally
connected to the OCI logic to monitor instruction fetch
activity. The fetch signal is active when Core8051
performs an instruction fetch, and the flush signal is
active when Core8051 fetches the first instruction after a
branch instruction.
The following signals are used to connect Core8051 to
optional external RAM devices for debug mode trace
memory control: TraceA, TraceDI, TraceDO, and TraceWr.
Example wrapper RTL source code is provided with the
RTL and Netlist releases of Core8051 to illustrate the
connection of the ProASIC PLUS and Axcelerator RAM cells
that are used as optional trace memory.
Access to ACC (Accumulator) Register
The external debugger hardware and software can
observe the contents of the ACC register by way of the
optional OCI logic block (through the JTAG interface).
The OCI can monitor the external memory address and
data buses (memaddr, memdatai, memdatao) to monitor
the program execution. The buses to and from internal
data memory (ramaddr, ramdatao, ramdatai) are also
visible for monitoring.
Ordering Information
Order Core8051 through your local Actel sales representative. Use the following numbering convention when
Table 44 ? Ordering Codes
XX
EV
SN
AN
SR
AR
UR
Description
Evaluation Version
Netlist for single-use on Actel devices
Netlist for unlimited use on Actel devices
RTL for single-use on Actel devices
RTL for unlimited use on Actel devices
RTL for unlimited use and not restricted to Actel devices
v6.0
39
相关PDF资料 |
PDF描述 |
|---|---|
| COREFFT-RM | IP MODULE COREFFT |
| COREFIR-RM | IP MODULE COREFIR |
| COREPCIF-RM | IP MODULE COREPCIF |
| COREU1LL-AR | IP MODULE COREU1LL |
| COREU1PHY-AR | IP MODULE COREU1PHY |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CORE8051-EV | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-SN | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-SR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-UR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-XX | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
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