参数资料
| 型号： | CORE8051-AR |
| 厂商： | Microsemi SoC |
| 文件页数： | 28/41页 |
| 文件大小： | 0K |
| 描述： | IP MODULE CORE8051 |
| 标准包装： | 1 |
| 系列： | * |
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Core8051
Table 20 ? psw Bit Functions
Ports
Bit
Symbol Function
Ports p0, p1, p2, and p3 are SFRs. The contents of the SFR
7
6
5
4
3
2
1
0
cy
ac
f0
rs1
rs0
ov
–
p
Carry flag
Auxiliary carry flag for BCD operations
General purpose flag 0 available for user
Register bank select control bit 1, used to
select working register bank
Register bank select control bit 0, used to
select working register bank
Overflow flag
User defined flag
Parity flag, affected by hardware to
indicate odd / even number of "one" bits
in the accumulator, i.e. even parity
can be observed on corresponding pins on the chip.
Writing a logic 1 to any of the ports causes the
corresponding pin to be at a high level (logic 1), and
writing a logic 0 causes the corresponding pin to be held
at a low level (logic 0).
All four ports on the chip are bidirectional. Each bit of
each port consists of a register, an output driver, and an
input buffer. Core8051 can output or read data through
any of these ports if they are not used for alternate
purposes.
When a read-modify-write instruction is being
performed, a port read will return the value of the
output register bits of the port. When a read-modify-
write instruction is not being performed, a port read will
return the value of the input bits of the port.
The state of bits rs1 and rs0 from the psw register select
Table 21 ? rs1/rs0 Bit Selections
Timers/Counters
rs1/rs0
00
01
10
11
Bank selected
Bank 0
Bank 1
Bank 2
Bank 3
Location
(00H – 07H)
(08H – 0FH)
(10H – 17H)
(18H – 1FH)
Timers 0 and 1
Core8051 has two 16-bit timer/counter registers: Timer 0
and Timer 1. Both can be configured for counter or timer
operations.
In timer mode, the register is incremented every machine
cycle, which means that it counts up after every 12
oscillator periods.
Stack Pointer (sp)
The stack pointer is a one-byte register initialized to 07H
after reset. This register is incremented before PUSH and
CALL instructions, causing the stack to begin at location
08H.
Data Pointer (dptr)
The data pointer (dptr) is two bytes wide. The lower part
is DPL, and the highest is DPH. It can be loaded as a two-
byte register (MOV DPTR,#data16) or as two registers
(e.g. MOV DPL,#data8). It is generally used to access
external code or data space (e.g. MOVC A,@A+DPTR or
MOV A,@DPTR respectively).
Program Counter (pc)
The program counter is two bytes wide, and is initialized
to 0000H after reset. This register is incremented during
fetching operation code or operation data from program
memory.
In counter mode, the register is incremented when a
falling edge is observed at the corresponding t0 or t1
input pin. Since it takes two machine cycles to recognize
a logic 1 to logic 0 transition event, the maximum input
count rate is 1/24 of the oscillator (clk input pin)
frequency. There are no restrictions on the duty cycle.
However, an input should be stable for at least one
machine cycle (12 clock periods) to ensure proper
recognition of a logic 0 or logic 1 value.
Four operating modes can be selected for Timer 0 and
Timer 1. Two SFRs (tmod and tcon) are used to select the
appropriate mode. The various register flags, bit
28
v6.0
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| COREFIR-RM | IP MODULE COREFIR |
| COREPCIF-RM | IP MODULE COREPCIF |
| COREU1LL-AR | IP MODULE COREU1LL |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CORE8051-EV | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-SN | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-SR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-UR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-XX | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
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