参数资料
型号: CORE8051-AR
厂商: Microsemi SoC
文件页数: 30/41页
文件大小: 0K
描述: IP MODULE CORE8051
标准包装: 1
系列: *
Core8051
Table 26 displays the tcon register bit functions.
Table 26 ? tcon Register Bit Functions
Bit
Symbol Function
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Timer 1 overflow flag. This flag is set when Timer 1 overflows. This flag should be cleared by the user’s software.
Timer 1 Run control bit. If cleared, Timer 1 stops.
Timer 0 overflow flag. This flag is set when Timer 0 overflows. This flag should be cleared by the user’s software.
Timer 0 Run control bit. If cleared, Timer 0 stops.
Interrupt 1 edge flag. This flag is set when a falling edge on the external pin int1 is observed. This flag is cleared
when an interrupt is processed.
Interrupt 1 type control bit. This bit selects whether a falling edge or a low level on input pin int1 causes an
interrupt.
Interrupt 0 edge flag. This flag is set when a falling edge on the external pin int0 is observed. This flag is cleared
when an interrupt is processed.
Interrupt 0 type control bit. This bit selects whether a falling edge or a low level on input pin int0 causes an
interrupt.
Serial Interface
Serial Port 0
The serial buffer consists of two separate registers:
transmit buffer and receive buffer. Writing data to the
SFR sbuf sets this data in the serial output buffer and
starts the transmission. Reading from the sbuf register
reads data from the serial receive buffer.
On receive, a start bit synchronizes the transmission,
eight data bits are available by reading the sbuf register,
and a stop bit sets the flag RB8 in the SFR scon.
Mode 2
This mode is similar to Mode 1 but has two main
differences. The baud rate is fixed at 1/32 or 1/64 of the
oscillator (clk input) frequency, and the following 11 bits
are transmitted or received:
The serial port can simultaneously transmit and receive
data. It can also buffer one byte at receive, which
?
?
One Start Bit (0)
Eight Data Bits (LSB first)
prevents the receive data from being lost if the CPU
reads the first byte before transmission of the second
byte is completed.
The serial port can operate in one of four modes.
Mode 0
In this mode, the rxd0i pin receives serial data and the
rxd0o pin transmits serial data. The txd0 pin outputs the
shift clock. Eight bits are transmitted with LSB first. The
baud rate is fixed at 1/12 of the crystal (clk input)
frequency.
Mode 1
In this mode, the rxd0i pin receives serial data and the
txd0 pin transmits serial data. No external shift clock is
used, and the following 10 bits are transmitted:
? One Programmable Ninth Bit
? One Stop Bit (1)
The ninth bit can be used to control the parity of the
serial interface. At transmission, the TB8 bit in the scon
register is output as the ninth bit, and at receive, the
ninth bit affects the RB8 bit in the SFR scon.
Mode 3
The only difference between Mode 2 and Mode 3 is that
the baud rate is variable in Mode 3. Reception is
initialized in Mode 0 by setting the RI flag in the scon
register to logic 0 and the REN flag in the scon register to
logic 1. In other modes, if the REN flag is a logic 1, the
reception of serial data will begin with a start bit.
30
?
?
?
One Start Bit (always 0)
Eight Data Bits (LSB first)
One Stop Bit (always 1)
v6.0
Multiprocessor Communication
The nine-bit reception feature in Modes 2 and 3 can be
used for multiprocessor communication. In this case, the
SM2 bit in the scon register is set to logic 1 by the slave
processors. When the master processor outputs the slave
address, it sets the ninth bit to logic 1, causing a serial
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