参数资料
| 型号： | CORE8051-AR |
| 厂商： | Microsemi SoC |
| 文件页数： | 9/41页 |
| 文件大小： | 0K |
| 描述： | IP MODULE CORE8051 |
| 标准包装： | 1 |
| 系列： | * |
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Core8051
Program Memory
Core8051 can address up to 64kB of program memory
space, from 0000H to FFFFH. The External Bus Interface
services program memory when the mempsrd signal is
active. Program memory is read when the CPU performs
fetching instructions or MOVC.
After reset, the CPU starts program execution from
location 0000H. The lower part of the program memory
includes interrupt and reset vectors. The interrupt
vectors are spaced at eight-byte intervals, starting from
0003H.
Program memory can be implemented as Internal RAM,
External RAM, External ROM, or a combination of all
three.
External Data Memory
Core8051 can address up to 64kB of external data
memory space, from 0000H to FFFFH. The External Bus
Interface services data memory when the memrd signal is
Table 6 ? Stretch Memory Cycle Width
active. Writing to external program memory is only
supported in debug mode using the OCI logic block and
external debugger hardware and software. Core8051
writes into external data memory when the CPU
executes MOVX @Ri,A or MOVX @DPTR,A instructions.
The external data memory is read when the CPU
executes MOVX A,@Ri or MOVX A,@DPTR instructions.
There is improved variable length of the MOVX
instructions to access fast or slow external RAM and
external peripherals. The three low-ordered bits of the
ckcon register control stretch memory cycles. Setting
ckcon stretch bits to logic 1 values enables access to very
slow external RAM or external peripherals.
change when stretch values are set from zero to seven.
The widths of the signals are counted in clk cycles. The
reset state of the ckcon register has a stretch value equal
to one (001), which enables MOVX instructions to be
performed with a single stretch clock cycle inserted.
ckcon Register
Read Signal Width
Write Signal Width
ckcon.2
0
0
0
0
1
1
1
1
ckcon.1
0
0
1
1
0
0
1
1
ckcon.0
0
1
0
1
0
1
0
1
Stretch Value
0
1
2
3
4
5
6
7
memaddr
1
2
3
4
5
6
7
8
memrd
1
2
3
4
5
6
7
8
memaddr
2
3
4
5
6
7
8
9
memwr
1
1
2
3
4
5
6
7
There are two types of instructions; one provides an 8-bit
address to the external data RAM, the other a 16-bit
indirect address to the external data RAM.
In the first instruction type, the contents of R0 or R1 in
the current register bank provide an 8-bit address. The
eight high ordered bits of address are stuck at zero.
Eight bits are sufficient for external l/O expansion
decoding or a relatively small RAM array. For somewhat
larger arrays, any output port pins can be used to output
higher-order address bits. These pins are controlled by an
output instruction preceding the MOVX.
In the second type of MOVX instructions, the data
pointer generates a 16-bit address. This form is faster
and more efficient when accessing very large data arrays
(up to 64kB), since no additional instructions are needed
to set up the output ports.
In some situations, it is possible to mix the two MOVX
types. A large RAM array, with its high-order address
lines, can be addressed via the data pointer or with code
v6.0
to output high-order address bits to any port followed
by a MOVX instruction using R0 or R1.
Internal Data Memory
The internal data memory interface services up to 256
bytes of off-core data memory. The internal data
memory address is always one byte wide. The memory
space is 256 bytes large (00H to FFH) and can be accessed
by direct or indirect addressing. The SFRs occupy the
upper 128 bytes. This SFR area is available only by direct
addressing. Indirect addressing accesses the upper 128
bytes of internal RAM.
The lower 128 bytes contain work registers and bit-
addressable memory. The lower 32 bytes form four banks
of eight registers (R0-R7). Two bits on the program
memory status word (PSW) select which bank is in use.
The next 16 bytes form a block of bit-addressable
memory space at bit addressees 00H-7FH. All of the bytes
9
相关PDF资料 |
PDF描述 |
|---|---|
| COREFFT-RM | IP MODULE COREFFT |
| COREFIR-RM | IP MODULE COREFIR |
| COREPCIF-RM | IP MODULE COREPCIF |
| COREU1LL-AR | IP MODULE COREU1LL |
| COREU1PHY-AR | IP MODULE COREU1PHY |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CORE8051-EV | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-SN | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-SR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-UR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
| CORE8051-XX | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051 |
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