参数资料
| 型号： | DS3106LN+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 15/92页 |
| 文件大小： | 0K |
| 描述： | IC TIMING LINE CARD 64-LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 160 |
| 类型： | 定时卡 IC，多路复用器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，Stratum，电信 |
| 输入： | CMOS，TTL |
| 输出： | CMOS，LVDS，LVPECL，TTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 312.5MHz |
| 电源电压： | 1.62 V ~ 1.98 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
| 产品目录页面： | 1429 (CN2011-ZH PDF) |
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DS3106
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7.7.1.3 Locked State
The T0 DPLL state machine can reach the locked state from the prelocked, prelocked 2, or loss-of-lock states
when the DPLL has locked to the selected reference for at least 2 seconds (see Section 7.7.5). In the locked state
the output clocks track the phase and frequency of the selected reference.
If the MCR1.LOCKPIN bit is set, the LOCK pin is driven high when the T0 DPLL is in the locked state.
While in the locked state, if the selected reference becomes inactive and an activity alarm is raised (corresponding
ACT bit set in the ISR2 register), the selected reference is marked invalid (ICn bit goes low in the VALSR1
register), and the LOS pin is asserted. If the input stays inactive for 2 seconds, the state machine transitions to the
holdover state. If the DPLL is switched to the other input and that input is active, the state machine transitions to
the prelocked 2 state.
7.7.1.4 Loss-of-Lock State
When the loss-of-lock detectors (see Section 7.7.5) indicate loss-of-phase lock, the state machine immediately
transitions from the locked state to the loss-of-lock state. If phase lock is regained during that period for more than
2 seconds while in the loss-of-lock state, the state machine transitions back to the locked state.
While in the loss-of-lock state, if the selected reference is becomes inactive, an activity alarm is raised
(corresponding ACT bit set in the ISR2 register), the selected reference is marked invalid (ICn bit goes low in the
VALSR1 register), and the LOS pin is asserted. If the input stays inactive for 2 seconds, the state machine
transitions to the holdover state. If the DPLL is switched to the other input and that input is active, the state
machine transitions to the prelocked 2 state.
7.7.1.5 Prelocked 2 State
The prelocked and prelocked 2 states are similar. If phase lock (see Section 7.7.5) is achieved for more than 2
seconds, the state machine transitions to locked mode. While in the prelocked 2 state, if the selected reference is
becomes inactive, an activity alarm is raised (corresponding ACT bit set in the ISR2 register), the selected
reference is marked invalid (ICn bit goes low in the VALSR1 register), and the LOS pin is asserted. If the input
stays inactive for 2 seconds, the state machine transitions to the holdover state.
7.7.1.6 Holdover State
The device reaches the holdover state when it declares its selected reference invalid for 2 seconds. During
holdover the T0 DPLL is not phase-locked to any input clock but instead generates its output frequency based on
previous frequencies while it was locked. When the selected reference becomes active, the state machine
immediately transitions from holdover to the prelocked 2 state, and tries to lock to the selected reference.
7.7.1.6.1Automatic Holdover
For automatic holdover (FRUNHO = 0 in MCR3), the device can be further configured for instantaneous mode or
averaged mode. In instantaneous mode (AVG = 0 in HOCR3), the holdover frequency is set to the DPLL’s current
frequency 50ms to 100ms before entry into holdover (i.e., the value of the FREQ field in the FREQ1, FREQ2, and
FREQ3 registers). The FREQ field is the DPLL’s integral path and, therefore, is an average frequency with a rate of
change inversely proportional to the DPLL bandwidth. The DPLL’s proportional path is not used in order to
minimize the effect of recent phase disturbances on the holdover frequency.
In averaged mode (AVG = 1 in HOCR3 and FRUNHO = 1 in MCR3), the holdover frequency is set to an internally
averaged value. During locked operation the frequency indicated in the FREQ field is internally averaged over a
one-second period. The T0 DPLL indicates that it has acquired a valid holdover value by setting the HORDY status
bit in MSR4 (latched status). If the T0 DPLL must enter holdover before the one-second average is available, an
instantaneous value 50ms to 100ms old from the integral path is used instead.
7.7.1.6.2Free-Run Holdover
For free-run holdover (FRUNHO = 1 in MCR3), the output frequency accuracy is generated with the accuracy of
the external oscillator frequency. The actual frequency is the frequency of the external oscillator plus the value of
the MCLK offset specified in the MCLKFREQ field in registers MCLK1 and MCLK2 (see Section 7.3). When
MCR3.FRUNHO is set the HOCR3:AVG bit is ignored.
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相关代理商/技术参数 |
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| DS3106LN+ | 功能描述:计时器和支持产品 Line Card Timing IC RoHS:否 制造商:Micrel 类型:Standard 封装 / 箱体:SOT-23 内部定时器数量:1 电源电压-最大:18 V 电源电压-最小:2.7 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Reel |
| DS3107FP000 | 制造商:Thomas & Betts 功能描述:30A,CON,2P3W,MG,107,125V |
| DS3107FRAB0 | 制造商:Thomas & Betts 功能描述:30A,REC,2P3W,MG,107,AB0,125,SC |
| DS3107MP000 | 制造商:Thomas & Betts 功能描述:30A,PLG,2P3W,MG,107,125V |
| DS3107MP00K | 制造商:Thomas & Betts 功能描述:30A,PLG,2P3W,MG,107,125V,CC |
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