参数资料
| 型号： | DS3106LN+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 8/92页 |
| 文件大小： | 0K |
| 描述： | IC TIMING LINE CARD 64-LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 160 |
| 类型： | 定时卡 IC，多路复用器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，Stratum，电信 |
| 输入： | CMOS，TTL |
| 输出： | CMOS，LVDS，LVPECL，TTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 312.5MHz |
| 电源电压： | 1.62 V ~ 1.98 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
| 产品目录页面： | 1429 (CN2011-ZH PDF) |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页
DS3106
16
7.4.2.1 Direct Lock Mode
In direct lock mode, the T0 DPLL locks to the selected reference at the frequency specified in the corresponding
ICR register. Direct lock mode can only be used for input clocks with these specific frequencies: 2kHz, 4kHz, 8kHz,
1.544MHz, 2.048MHz, 5MHz, 6.312MHz, 6.48MHz, 19.44MHz, 25.92MHz, 31.25MHz, 38.88MHz, 51.84MHz, and
77.76MHz. The DIVN mode can be used to divide an input down to any of these frequencies except 155.52MHz.
MTIE figures may be marginally better in direct lock mode because the higher frequencies allow more frequent
phase updates.
7.4.2.2 Alternate Direct Lock Mode
Alternate direct lock mode is the same as direct lock mode except an alternate list of direct lock frequencies is used
(see the FREQ field definition in the ICR register description). The alternate frequencies are included to support
clock rates found in Ethernet, CMTS, wireless, and GPS applications. The alternate frequencies are: 10MHz,
25MHz, 62.5MHz, and 125MHz. The frequencies 62.5MHz and 125MHz are internally divided down to 31.25MHz,
while 10MHz and 25MHz are internally divided down to 5MHz.
7.4.2.3 LOCK8K Mode
In LOCK8K mode, an internal divider is configured to divide the selected reference down to 8kHz. The DPLL locks
to the 8kHz output of the divider. LOCK8K mode can only be used for input clocks with the standard direct lock
frequencies: 8kHz, 1.544MHz, 2.048MHz, 5MHz, 6.312MHz, 6.48MHz, 19.44MHz, 25.0MHz, 25.92MHz,
31.25MHz, 38.88MHz, 51.84MHz, 62.5MHz, and 77.76MHz. LOCK8K mode is enabled for a particular input clock
by setting the LOCK8K bit in the corresponding ICR register.
LOCK8K mode gives a greater tolerance to input jitter when the multicycle phase detector is disabled because it
uses lower frequencies for phase comparisons. The clock edge to lock to on the selected reference can be
configured using the 8KPOL bit in the TEST1 register. For 2kHz and 4kHz clocks the LOCK8K bit is ignored and
direct-lock mode is used.
7.4.2.4 DIVN Mode
In DIVN mode, an internal divider is configured from the value stored in the DIVN registers. The DIVN value must
be chosen so that when the selected reference is divided by DIVN+1, the resulting clock frequency is the same as
the standard direct lock frequency selected in the FREQ field of the ICR register. The DPLL locks to the output of
the divider. DIVN mode can only be used for input clocks whose frequency is less than or equal to 125MHz. The
DIVN register field can range from 0 to 65,535 inclusive. The same DIVN+1 factor is used for all input clocks
configured for DIVN mode.
7.5
Input Clock Monitoring
Each input clock is continuously monitored for activity. Activity monitoring is described in Sections 7.5.2 and 7.5.3.
The valid/invalid state of each input clock is reported in the corresponding real-time status bit in register VALSR1.
When the valid/invalid state of a clock changes, the corresponding latched status bit is set in register MSR1, and
an interrupt request occurs if the corresponding interrupt enable bit is set in register IER1. Input clocks marked
invalid cannot be automatically selected as the reference for either DPLL.
7.5.1 Frequency Monitoring
The DS3106 monitors the frequency of each input clock and invalidates any clock whose frequency is more than
10,000ppm away from nominal. The frequency range monitor can be disabled by clearing the MCR1.FREN bit. The
frequency range measurement uses the internal 204.8MHz master clock as the frequency reference.
7.5.2 Activity Monitoring
Each input clock is monitored for activity and proper behavior using a leaky bucket accumulator. A leaky bucket
accumulator is similar to an analog integrator: the output amplitude increases in the presence of input events and
相关PDF资料 |
PDF描述 |
|---|---|
| DS3231MZ+ | IC RTC I2C 8SOIC |
| DS3231SN#T&R | IC RTC W/TCXO 16-SOIC |
| DS3232MZ+ | IC RTC W/SRAM I2C 8SOIC |
| DS3232SN#T&R | IC RTC W/TCXO 20-SOIC |
| DS3234S# | IC RTC W/TCXO 20-SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3106LN+ | 功能描述:计时器和支持产品 Line Card Timing IC RoHS:否 制造商:Micrel 类型:Standard 封装 / 箱体:SOT-23 内部定时器数量:1 电源电压-最大:18 V 电源电压-最小:2.7 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Reel |
| DS3107FP000 | 制造商:Thomas & Betts 功能描述:30A,CON,2P3W,MG,107,125V |
| DS3107FRAB0 | 制造商:Thomas & Betts 功能描述:30A,REC,2P3W,MG,107,AB0,125,SC |
| DS3107MP000 | 制造商:Thomas & Betts 功能描述:30A,PLG,2P3W,MG,107,125V |
| DS3107MP00K | 制造商:Thomas & Betts 功能描述:30A,PLG,2P3W,MG,107,125V,CC |
发布紧急采购，3分钟左右您将得到回复。