DS3106LN+ (Maxim) PDF资料下载 Datasheet(61/92 页)

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参数资料

型号：	DS3106LN+
厂商：	Maxim Integrated Products
文件页数：	61/92页
文件大小：	0K
描述：	IC TIMING LINE CARD 64-LQFP
产品培训模块：	Lead (SnPb) Finish for COTS Obsolescence Mitigation Program
标准包装：	160
类型：	定时卡 IC，多路复用器
PLL：	是
主要目的：	以太网，SONET/SDH，Stratum，电信
输入：	CMOS，TTL
输出：	CMOS，LVDS，LVPECL，TTL
电路数：	1
比率 - 输入:输出：	2:2
差分 - 输入:输出：	无/是
频率 - 最大：	312.5MHz
电源电压：	1.62 V ~ 1.98 V
工作温度：	-40°C ~ 85°C
安装类型：	表面贴装
封装/外壳：	64-LQFP
供应商设备封装：	64-LQFP（10x10）
包装：	托盘
产品目录页面：	1429 (CN2011-ZH PDF)

DS3106

T0CR1

T0 DPLL Configuration Register 1

65h

Bit #

Name

—

T4APT0

T0FT4[2:0]

T0FREQ[2:0]

Default

see below

Bit 6: T4 APLL Source from T0 (T4APT0). When this bit is set to 0, T4CR1:T4FREQ configures the T4 APLL DFS

frequency. The T4 APLL DFS frequency affects the frequency of the T4 APLL, which, in turn, affects the available

output frequencies on the output clock pins (see the OCR registers). When this bit is set to 1, the frequency of the

T4 APLL DFS is configured by the T0CR1:T0FT4[2:0] field below. See Section 7.8.2.

0 = T4 APLL frequency is determined by T4FREQ.

1 = T4 APLL frequency is determined by T0FT4.

Bits 5 to 3: T0 Frequency to T4 APLL (T0FT4[2:0]). When the T4APT0 bit is set to 1, this field specifies the

frequency of the T4 APLL DFS. This frequency can be different than the frequency specified by T0CR1:T0FREQ.

See Section 7.8.2.

T0FT4

T4 APLL DFS FREQUENCY

T4 APLL FREQUENCY (4 x T4 APLL DFS)

000 =

24.576MHz (12 x E1)

98.304MHz (48 x E1)

001 =

62.500MHz (GbE

÷ 16)

250.000MHz (GbE

÷ 4)

010 =

32.768MHz (16 x E1)

131.072MHz (64 x E1)

011 =

{unused value}

100 =

37.056MHz (24 x DS1)

148.224MHz (96 x DS1)

101 =

{unused value}

110 =

24.704MHz (16 x DS1)

98.816MHz (64 x DS1)

111 =

25.248MHz (4 x 6312kHz)

100.992MHz (16 x 6312kHz)

Bits 2 to 0: T0 DPLL Output Frequency (T0FREQ[2:0]). This field configures the T0 APLL DFS frequency. The

T0 APLL DFS frequency affects the frequency of the T0 APLL, which, in turn, affects the available output

frequencies on the output clock pins (see the OCR registers). See Section 7.8.2. The default frequency is

controlled by the O6F[2:0] and O3F[2:0] pins as described in Table 7-14.

T0FREQ

T0 APLL DFS FREQUENCY

T0 APLL FREQUENCY (4 x T0 APLL DFS)