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参数资料
| 型号： | DS3148N |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 13/89页 |
| 文件大小： | 0K |
| 描述： | IC 8CH DS3/3 FRAMER 349-BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 控制器类型： | DS3/E3 调帧器 |
| 接口： | LIU |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 640mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 349-BGA 裸露焊盘 |
| 供应商设备封装： | 349-HCBGA（27x27） |
| 包装： | 托盘 |
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DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
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7.4 Error Insertion
Errors can be created in the transmit overhead and line coding for diagnostic purposes. These errors do not cause
any loss of data when created. The T3E3EIC error insertion register contains all of the control bits to create errors.
The TMEI input pin can also be used to create errors.
7.5 Loopbacks
7.5.1 Line Loopback
The line loopback connects the incoming DS3/E3 data (RCLK, RPOS/RNRZ, and RNEG inputs) directly back to
the transmit side (TCLK, TPOS/TNRZ, and TNEG outputs). When this loopback is enabled, the incoming data
continues to pass through the receive framer block, but the output data from the transmit formatter is ignored. See
Figure 1-1 for a visual description of this loopback. Setting the LLB bit in the MC2 register activates the line
loopback.
7.5.2 Diagnostic Loopback
The diagnostic loopback sends the outgoing DS3/E3 data directly back to the receive side. When this loopback is
enabled, the incoming receive data at RCLK, RPOS, and RNEG is ignored. See Figure 1-1 for a visual description
of this loopback. During diagnostic loopback the device can simultaneously generate AIS at the TCLK, TPOS, and
TNEG outputs, while regular traffic is looped back to the receiver. This feature keeps the diagnostic signal that is
being looped back from disturbing downstream equipment. Setting the DLB bit in the MC2 register activates the
diagnostic loopback.
7.5.3 Payload Loopback
The payload loopback sends the DS3/E3 payload from the receive framer back to the transmit formatter. When this
loopback is enabled, the incoming receive data continues to be present on the RDAT pin, but the transmit data on
the TDAT pin is ignored. During payload loopback, the TSOF and TDEN signals are realigned to the receive frame,
and the signals at TOH and TOHEN are active and can still overwrite any bit position. See Figure 1-1 for a visual
description of this loopback. During payload loopback TSOF, TDEN, TOHEN, and TOH are aligned to the ROCLK
signal. When PLB and DLB are both set, diagnostic loopback takes precedence. Setting the PLB bit in the MC2
register activates payload loopback.
7.5.4 BERT and Loopback Interaction
Table 7-A describes how the payload bits move through the device with various combinations of BERT modes and
loopbacks active. The BERT mode is set in the BM[1:0] bits in the BCR1 register. The BERT is enabled when the
BENA bit is set in the BCR1 register. Table 7-B describes how the overhead bits move through the device with
various combinations of BERT modes and loopbacks active.
Table 7-A. BERT/Loopback Interaction—Payload Bits
CONFIGURATION BITS
BITS AT PAYLOAD BIT POSITIONS
DLB
LLB
PLB
BM [1:0]
From RPOS/RNEG To:
From TDAT To:
From BERT To:
0
0X
BERT and RDAT
Not used
TPOS/TNEG
0
1X
Not used
BERT and TPOS/TNEG
RDAT
1
0
0X
Not used
TPOS/TNEG, BERT, and
RDAT
1
0
1X
Not used
BERT and TPOS/TNEG
RDAT
0
1
0
0X
TPOS/TNEG, RDAT, and
BERT
Not used
0
1
0
1X
TPOS/TNEG
BERT
RDAT
0
1
00
TPOS/TNEG and RDAT
and BERT
Not used
0
1
01
RDAT and BERT
Not used
TPOS/TNEG
0
1
1X
TPOS/TNEG
BERT
RDAT
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