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参数资料
| 型号： | DS3148N |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 60/89页 |
| 文件大小： | 0K |
| 描述： | IC 8CH DS3/3 FRAMER 349-BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 控制器类型： | DS3/E3 调帧器 |
| 接口： | LIU |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 640mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 349-BGA 裸露焊盘 |
| 供应商设备封装： | 349-HCBGA（27x27） |
| 包装： | 托盘 |
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DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
63 of 89
Register Name:
THDLC1
Register Description:
Transmit HDLC FIFO Data
Register Address:
5Eh
Bit #
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0
Note 1: The host processor should always write to THDLC1 first followed by THDLC2. Writing to THDLC2 latches the data from both THDLC1
and THDLC2 into the transmit FIFO.
Note 2: THDLC1 and THDLC2 are write-only registers. Data read from these registers is undefined.
Note 3: The transmit FIFO can be filled to a maximum capacity of 256 bytes. When the transmit FIFO is full, it does not latch additional data.
Bits 0 to 7: Transmit FIFO Data (D[7:0]). Data for the transmit FIFO is written to these bits. D0 is the LSB and is
transmitted first, while D7 is the MSB and is transmitted last.
Register Name:
THDLC2
Register Description:
Transmit HDLC FIFO Status
Register Address:
5Fh
Bit #
7
6
5
4
3
2
1
0
Name
N/A
TMEND
Default
—
0
Bit 0: Transmit Message End (TMEND). This bit is used to delineate packets in the transmit FIFO. It should be
set to 1 when the last byte of a message is written to the THDLC1 register. When set to 1, TMEND indicates that
the message is complete and that the HDLC controller should calculate and append the CRC checksum (FCS) and
at least two flags (7Eh). This bit should be set to 0 for all other data written to the FIFO. All outgoing HDLC
messages must be at least two bytes in length.
7.11 FEAC Controller
The DS3 C-Bit Parity far-end alarm and control (FEAC) channel carries repeating 16-bit codewords of the form
0xxxxxx011111111 (rightmost bit transmitted first), where x can be 0 or 1. These codewords are used to send
alarm or status information from the far end to the near end, and send loopback commands to the far end.
Each DS314x framer contains an on-board FEAC controller. When the framer is in DS3 C-Bit Parity mode, the
FEAC controller sources and sinks the FEAC channel (the third C-bit in M-subframe 1). When the framer is in E3
mode, the FEAC receiver is always connected to the E3 national bit (Sn, bit 12 of the E3 frame). If the host
processor does not wish to use the FEAC controller for processing the E3 national bit, then it should ignore the
status provided by the FEAC receiver. The FEAC transmitter can be provisioned to source the E3 national bit by
setting T3E3CR1:E3SnC[1:0] = 10. The FEAC controller is not used in DS3 M23 framing mode.
The FEAC transmitter can be configured to transmit one codeword 10 times, one codeword continuously, or one
codeword 10 times followed by another codeword 10 times. This last option is useful for sending loopback
commands where the loopback activate/deactivate command must be followed by the code for line to be looped
back. FEAC codewords are transmitted at least 10 times. When the FEAC transmitter is not sending codewords, it
enters the idle state where it transmits all ones on the FEAC channel and sets the transmit FEAC idle bit (FSR:TFI)
to 1.
The FEAC receiver does a bit-by-bit search for a data pattern matching the form of a FEAC codeword. When a
codeword is found, the receiver validates the codeword by checking to see that the same codeword is found in
three consecutive opportunities. After a codeword is validated, the receiver sets the receive FEAC codeword detect
status bit (FSR:RFCD) and writes the codeword into the receive FEAC FIFO for the host processor to read. The
host processor can use the RFCD or receive FEAC FIFO empty (RFFE) status bits to know when to read the
receive FEAC FIFO. The receive FEAC FIFO is four codewords deep. If the FIFO is full when the FEAC receiver
attempts to write a new codeword, the new codeword is discarded and the receive FEAC FIFO Overflow status bit
(RFFOL) is set. The FEAC receiver clears the RFCD status bit when the valid codeword is no longer present on the
FEAC channel (i.e., when a different codeword is received twice in a row).
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