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参数资料
| 型号： | DS3148N |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 42/89页 |
| 文件大小： | 0K |
| 描述： | IC 8CH DS3/3 FRAMER 349-BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 控制器类型： | DS3/E3 调帧器 |
| 接口： | LIU |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 640mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 349-BGA 裸露焊盘 |
| 供应商设备封装： | 349-HCBGA（27x27） |
| 包装： | 托盘 |
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DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
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Register Name:
BCR1
Register Description:
BERT Control Register 1
Register Address:
30h
Bit #
7
6
5
4
3
2
1
0
Name
BM1
BM0
BENA
TINV
RINV
RESYNC
TC
LC
Default
0
Bit 0: Load Bit and Error Counts (LC). A low-to-high transition latches the current bit and error counts into the
host-processor-accessible registers BBCR and BBECR and then clears the internal counters. This bit should be
toggled from low to high whenever the host processor wishes to begin a new acquisition period. Must be cleared
and set again for subsequent loads.
Bit 1: Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator. This bit should be toggled
from low to high whenever the host processor loads a new pattern or needs to resynchronize to an existing pattern.
Must be cleared and set again for subsequent loads. For pseudorandom patterns, PS[2:0] must be configured
before toggling TC. For repetitive patterns, PS[2:0], RPL[3:0], and RP[31:0] must be configured before toggling TC.
For alternating word patterns, PS[2:0], AWC[7:0], and RP[31:0] must be configured before toggling TC.
Bit 2: Force Resynchronization (RESYNC). A low-to-high transition forces the receive BERT synchronizer to
resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host
processor wishes to acquire synchronization on a new pattern. Must be cleared and set again for a subsequent
resynchronization.
Bit 3: Receive Invert Data Enable (RINV)
0 = do not invert the incoming data stream
1 = invert the incoming data stream
Bit 4: Transmit Invert Data Enable (TINV)
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
Bit 5: BERT Enable (BENA). This bit is used to enable the BERT transmitter, replacing the payload, or the entire
DS3/E3 signal (depending on the setting of BM[1:0]). The BERT receiver is always enabled. Configure all BERT
control and pattern registers and toggle the TC control bit before setting BENA.
0 = disable BERT transmitter
1 = enable BERT transmitter
Bits 6, 7: BERT Mode (BM[1:0]). These bits select whether the BERT pattern replaces only the DS3/E3 payload
or the entire DS3/E3 frame (payload and overhead). These bits also select the BERT transmit direction: line side
(TPOS/TNEG and RPOS/RNEG) or equipment side (TDAT and RDAT).
BM[1:0]
DATA
TRANSMIT
RECEIVE
00
Payload
TPOS/TNEG
RPOS/RNEG
01
Entire frame
TPOS/TNEG
RPOS/RNEG
10
Payload
RDAT
TDAT
11
Entire frame
RDAT
TDAT
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS315 | 制造商:Hubbell Wiring Device-Kellems 功能描述:SWITCH, DECO SER, 3W, 15A 120/277V, BR |
| DS3150 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:3.3V, DS3/E3/STS-1 Line Interface Unit |
| DS3150DK | 功能描述:网络开发工具 DS3150 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| DS3150G | 功能描述:IC LIU T3/E3/STS-1 49-BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件 |
| DS3150GN | 功能描述:IC LIU T3/E3/STS-1 IND 49-BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件 |
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