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| 型号： | DS3148N |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 17/89页 |
| 文件大小： | 0K |
| 描述： | IC 8CH DS3/3 FRAMER 349-BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 控制器类型： | DS3/E3 调帧器 |
| 接口： | LIU |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 640mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 349-BGA 裸露焊盘 |
| 供应商设备封装： | 349-HCBGA（27x27） |
| 包装： | 托盘 |
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DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
24 of 89
Register Name:
MC2
Register Description:
Master Configuration Register 2
Register Address:
02h
Bit #
7
6
5
4
3
2
1
0
Name
OSTCS
TCCLK
N/A
RZSF
N/A
DLB
LLB
PLB
Default
0
—
0
Bit 0: Payload Loopback Enable (PLB). When payload loopback is enabled, the transmit formatter operates from
the receive clock (rather than TICLK) and sources DS3/E3 payload bits from the receive data stream rather than
from the TDAT input pin. Receive data is still available on the RDAT output pin during payload loopback. See
Figure 1-1 for a visual description of this loopback.
0 = disable payload loopback
1 = enable payload loopback
Bit 1: Line Loopback Enable (LLB). Line loopback connects the TPOS, TNEG, and TCLK output pins to the
RPOS, RNEG, and RCLK input pins. When line loopback is enabled, the receive framer continues to process the
incoming receive data stream and present it on the RDAT pin; the output of the transmit formatter is ignored. Line
loopback and diagnostic loopback can be active at the same time to support simultaneous local and far-end
loopbacks. See Figure 1-1 for a visual description of this loopback.
0 = disable line loopback
1 = enable line loopback
Bit 2: Diagnostic Loopback Enable (DLB). When diagnostic loopback is enabled, the receive framer sources
data from the transmit formatter rather than the RCLK, RPOS, and RNEG input pins. Transmit data is sourced prior
to transmit AIS generation, unframed all ones generation, TCLK/TPOS/TNEG pin inversion, and TPOS/TNEG
force-high logic. This allows the device to transmit AIS or unframed all ones to the far end while locally looping
back the actual transmit data stream, which could be test patterns or other traffic that should not be sent to the far
end. See Figure 1-1 for a visual description of this loopback.
0 = disable diagnostic loopback
1 = enable diagnostic loopback
Bit 4: Receive Zero Suppression Code Format (RZSF). When RZSF is set to logic 0, the B3ZS/HDB3 decoder
declares a B3ZS codeword when it sees a zero followed by a BPV that has the opposite polarity as the previous
BPV, and an HDB3 codeword when it sees two zeros followed by a BPV that has the opposite polarity as the
previous BPV. When RZSF is set to logic 1, the polarity of the previous BPV is not considered, and the decoder
declares a B3ZS codeword when it sees a zero followed by a BPV and an HDB3 codeword when it sees two zeros
followed by a BPV.
Bit 6: Transmit Constant Clock Select (TCCLK). When TCCLK is set to logic 1, the device outputs a constant
transmit clock on the TDEN/TGCLK pin instead of a data enable or gapped clock. This bit has precedence over the
0 = the function of the TDEN/TGCLK pin is controlled by TDENMS control bit
1 = the TDEN/TGCLK pin is a constant transmit clock output
Bit 7: One-Second Timer Clock Select (OSTCS). This control bit selects the clock source for the internal one-
second timer.
0 = use RCLK
1 = use TICLK
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