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参数资料
| 型号： | DS3148N |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 30/89页 |
| 文件大小： | 0K |
| 描述： | IC 8CH DS3/3 FRAMER 349-BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 控制器类型： | DS3/E3 调帧器 |
| 接口： | LIU |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 640mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 349-BGA 裸露焊盘 |
| 供应商设备封装： | 349-HCBGA（27x27） |
| 包装： | 托盘 |
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DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
36 of 89
Register Name:
T3E3EIC
Register Description:
DS3/E3 Error Insert Control Register
Register Address:
12h
Bit #
7
6
5
4
3
2
1
0
Name
MEIMS
FBEIC1
FBEIC0
FBEI
T3CPBEI
T3PBEI
EXZI
BPVI
Default
0
Bit 0: Bipolar Violation Insert (BPVI). A 0-to-1 transition on this bit causes a single BPV to be inserted into the
transmit data stream during the next occurrence of three consecutive 1s. This bit must be cleared and set again for
a subsequent BPV to be inserted. Toggling this bit has no effect when the LIU interface is in the binary mode. In
the manual error insert mode (MEIMS = 1), errors are inserted on each toggle of the TMEI input signal as long as
this bit is logic 1. When this bit is logic 0, no BPVs are inserted.
Bit 1: Excessive Zero Insert (EXZI). A 0-to-1 transition on this bit causes a single EXZ event to be inserted into
the transmit data stream. An EXZ event is defined as three or more consecutive 0s in the DS3 mode and four or
more consecutive 0s in the E3 mode. After this bit has been toggled from logic 0 to logic 1, the formatter
suppresses the next possible B3ZS/HDB3 codeword substitution to create the EXZ event. This bit must be cleared
and set again for a subsequent EXZ event to be inserted. Toggling this bit has no effect when the LIU interface is in
the binary mode. In the manual error insert mode (MEIMS = 1), errors are inserted on each toggle of the TMEI
input signal as long as this bit is logic 1. When this bit is logic 0, no EXZ events are inserted.
Bit 2: DS3 P-Bit Parity Error Insert (T3PBEI). A 0-to-1 transition on this bit causes a single DS3 P-bit parity error
event to be inserted into the transmit data stream. A DS3 P-bit parity error is defined as inverting both P bits in a
DS3 frame. Once this bit has been toggled from logic 0 to logic 1, the formatter flips both P bits in the next DS3
frame. This bit must be cleared and set again for a subsequent error to be inserted. Toggling this bit has no effect
when the framer is operated in the E3 mode. In the manual error insert mode (MEIMS = 1), errors are inserted on
each toggle of the TMEI input signal as long as this bit is logic 1. When this bit is logic 0, no P-bit parity errors are
inserted.
Bit 3: DS3 C-Bit Parity Error Insert (T3CPBEI). A 0-to-1 transition on this bit causes a single DS3 CP-bit parity
error event to be inserted into the transmit data stream. A DS3 CP-bit parity error is defined as inverting the proper
polarity of all three CP bits in a DS3 frame. Once this bit has been toggled from logic 0 to logic 1, the framer flips all
three CP bits in the next DS3 frame. This bit must be cleared and set again for a subsequent error to be inserted.
Toggling this bit has no effect when the framer is not operated in C-Bit Parity mode or when the framer is operated
in the E3 mode. In the manual error insert mode (MEIMS = 1), errors are inserted on each toggle of the TMEI input
signal as long as this bit is logic 1. When this bit is logic 0, no CP-bit parity errors are inserted.
Bit 4: Frame Bit-Error Insert (FBEI). A 0-to-1 transition on this bit causes the transmit framer to generate framing
bit errors. The type of framing bit error to be inserted is controlled by the FBEIC[1:0] bits. Once this bit has been
toggled from logic 0 to logic 1, the framer inserts framing bit errors in the next possible frame. This bit must be
cleared and set again for a subsequent error to be inserted. In the manual error insert mode (MEIMS = 1), errors
are inserted on each toggle of the TMEI input signal as long as this bit is logic 1. When this bit is logic 0, no frame
bit errors are inserted.
Bits 5, 6: Frame Bit-Error Insert Control Bits 0 and 1 (FBEIC[1:0])
FBEIC[1:0]
TYPE OF FRAMING BIT ERROR INSERTED
00
DS3 Mode: A single F-bit error
E3 Mode: A single FAS word of 1111110000 is generated instead of the normal FAS word, which is
1111010000 (i.e., only 1 bit inverted)
01
DS3 Mode: A single M-bit error
E3 Mode: A single FAS word of 0000101111 is generated instead of the normal FAS word, which is
1111010000 (i.e., all FAS bits are inverted)
10
DS3 Mode: Four consecutive F-bit errors (causes the far end to lose synchronization)
E3 Mode: Four consecutive FAS words of 1111110000 are generated instead of the normal FAS word,
which is 1111010000 (i.e., only 1 bit inverted; causes the far end to lose synchronization)
11
DS3 Mode: Three consecutive M-bit errors (causes the far end to lose synchronization)
E3 Mode: Four consecutive FAS words of 0000101111 are generated instead of the normal FAS word,
which is 1111010000 (i.e., all FAS bits are inverted; causes the far end to lose synchronization)
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