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| 型号： | DS3148N |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 2/89页 |
| 文件大小： | 0K |
| 描述： | IC 8CH DS3/3 FRAMER 349-BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 控制器类型： | DS3/E3 调帧器 |
| 接口： | LIU |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 640mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 349-BGA 裸露焊盘 |
| 供应商设备封装： | 349-HCBGA（27x27） |
| 包装： | 托盘 |
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DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
10 of 89
5.3 Transmit Formatter System Interface Pins
NAME
TYPE
FUNCTION
TICLK
I
Transmit Input Clock. TICLK samples the TDAT, TDEN/TGCLK, TSOF, TOH, and TOHEN input pins.
TICLK accepts a smooth clock or a gapped clock up to 52MHz. When the framer is connected to an LIU
without a jitter attenuator, TICLK should be an ungapped, transmission-quality DS3 or E3 clock (
±20ppm,
low jitter) to meet the frequency accuracy and jitter requirements for transmission. The default active
sampling edge of TICLK is the rising edge. To make the negative edge the active sampling edge, set
MC3:TICLKI = 1. When the TCSEL pin is high (common transmit clock mode) TICLK is not used and
should be wired low.
TDAT
I
Transmit Data Input. In C-Bit Parity DS3 mode, payload bits are clocked into the transmit formatter on
TDAT. In M23 DS3 mode and E3 mode, payload bits, stuff opportunity bits and C bits are clocked in on
TDAT. TDAT is sampled on the active sampling edge of TICLK. The default active sampling edge of
TICLK is the rising edge. To make the negative edge the active sampling edge, set MC3:TICLKI = 1.
TDAT can be internally inverted by setting MC3:TDATI = 1.
TDEN/
TGCLK
O
Transmit Data Enable/Transmit Gapped Clock. The transmit formatter can be configured to either output a
data enable (TDEN) or a gapped clock (TGCLK). In data enable mode, TDEN goes active when payload
data should be made available on the TDAT input pin and inactive when the formatter is inserting framing
overhead. In gapped clock mode, TGCLK acts as a demand clock for the TDAT input, toggling for each
payload bit position and not toggling when the formatter is inserting framing overhead. In DS3 mode,
overhead data is defined as the M bits, F bits, C bits, X bits, and P bits. In E3 mode, overhead data is
defined as the FAS word, RAI bit, and Sn bit (bits 1 to 12). To configure the transmit formatter for data
TDEN is normally active high; to make TDEN active low, set MC3:TDENI = 1. TGCLK normally is the
same polarity as TICLK; to invert TGCLK, set MC3:TDENI = 1. In the transmit pass-through mode
(T3E3CR1:TPT = 1), TDEN/TGCLK continues to mark the payload positions in the original frame
established before TPT was activated. This pin can also be made to output a constant transmit clock by
setting MC2:TCCLK = 1. This constant clock is useful for certain applications that need to use the TOH
and TOHEN pins during payload loopback.
TSOF
O/I
Transmit Start-of-Frame. TSOF indicates the DS3 or E3 frame boundary on the outgoing transmit data
stream. When TSOFC = 1 in the MC3 register, TSOF is an output and pulses high for one TICLK cycle
during the last bit of each DS3 or E3 frame. When TSOFC = 0, TSOF is an input and is sampled to set the
transmit DS3 or E3 frame boundary. See Figure 5-1 for functional timing. Note that the reset default is for
TSOF to be an input. Some applications require an external pullup or pulldown resistor on TSOF to keep it
from floating during power-up and reset. TSOF is normally active high. Set MC3:TSOFI = 1 to make TSOF
active low. If transmit pass-through (TPT) mode is enabled (T3E3CR1:TPT = 1) and TSOF is an output,
TSOF continues to mark the original frame position that was established before TPT activation.
TOHEN
I
Transmit Overhead Enable. Together the TOHEN and TOH pins make a simple, general-purpose
transmit-overwrite port. This port is usually used to overwrite overhead bit positions (such as unused C
bits in C-Bit Parity mode), but payload bits can be overwritten as well. During any clock cycle in which
TOHEN is active, the formatter sources the TOH pin rather than the TDAT pin or the internal overhead
generation logic. In DS3 mode, parity is not recalculated if any payload bits are overwritten. TOHEN can
be internally inverted by setting MC3:TOHENI = 1.
TOH
I
Transmit Overhead Data. Together the TOHEN and TOH pins make a simple, general-purpose transmit-
overwrite port. This port is usually used to overwrite overhead bit positions (such as unused C bits in C-Bit
Parity mode), but payload bits can be overwritten as well. During any clock cycle in which TOHEN is
active, the formatter sources the TOH pin rather than the TDAT pin or the internal overhead generation
logic. TOH can be inverted by setting MC3:TOHI = 1.
TMEI
I
Transmit Manual-Error Insert. This pin is used to manually control the insertion of errors in the DS3 or E3
frame structure or the line coding. This pin is enabled when MEIMS = 1 in the T3E3EIC register. A single
error is normally inserted on the rising edge of TMEI. The other bits in the T3E3EIC register control which
types of errors are inserted. All framers on the device share this pin.
TCCLK
I
Transmit Common Clock. This signal can be used by all of the framers as a common transmit clock,
replacing the signals on the TICLKn pins. Wiring the TCSEL pin high enables TCCLK. If TCCLK is
enabled, the TICLKIn control bit in the MC3 register can be used to provide an inverted version of this
signal to the transmit formatter on a per framer basis. The timing relationships between the transmit clock
and the transmit formatter signals changes slightly compared to the timing using the TICLKn pins. See
Section 11 for more information.
TCSEL
I
Transmit Common Clock Select. This signal is used to select the clock on the TCCLK pin as the common
transmit clock for all the framers, replacing the clocks on the TICLKn pins. When this pin is high, the
TCCLK signal clocks all the framers. When this pin is low, the TICLKn signals clock the framers
individually.
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