DS3148N (Maxim) PDF资料下载 Datasheet(28/89 页)

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参数资料

型号：	DS3148N
厂商：	Maxim Integrated Products
文件页数：	28/89页
文件大小：	0K
描述：	IC 8CH DS3/3 FRAMER 349-BGA
产品培训模块：	Lead (SnPb) Finish for COTS Obsolescence Mitigation Program
标准包装：	1
控制器类型：	DS3/E3 调帧器
接口：	LIU
电源电压：	3.135 V ~ 3.465 V
电流 - 电源：	640mA
工作温度：	-40°C ~ 85°C
安装类型：	表面贴装
封装/外壳：	349-BGA 裸露焊盘
供应商设备封装：	349-HCBGA（27x27）
包装：	托盘

DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers

34 of 89

Bit 3: DS3/E3 Transmit Alarm Indication Signal (TAIS). When this bit is logic 1 in DS3 mode, the transmitter

generates DS3 AIS, which is a properly F-bit and M-bit framed 1010... data pattern with both X bits set to 1, all C

bits set to 0, and the proper P bits. When this bit is logic 1 in E3 mode, the transmitter generates an unframed all-

ones pattern. When this bit is logic 0, normal data is transmitted.

0 = do not transmit AIS

1 = transmit AIS

Bit 4: DS3/E3 Transmit Remote Alarm Indication (TRAI). When this bit is logic 1 in DS3 mode, both X bits of

each DS3 frame are set to logic 0. When this bit is logic 1 in E3 mode, the RAI bit (bit 11 of each E3 frame) is set to

logic 1. When this bit is logic 0 in DS3 mode, both X bits are set to logic 1. When this bit is logic 0 in E3 mode, the

RAI bit is set to logic 0.

0 = do not transmit RAI

1 = transmit RAI

Bit 5: Transmit DS3 Idle Signal Enable (T3IDLE). When this bit is logic 1 in DS3 mode, the transmitter generates

the DS3 idle signal instead of the normal transmit data. The DS3 idle signal is defined as a normally DS3 framed

pattern (i.e., with the proper F bits and M bits along with the proper P bits) where the information bit fields are

completely filled with a data pattern of 1100..., the C bits in Subframe 3 are set to logic 0, and both X bits are set to

logic 1. In C-Bit Parity mode, the PMDL and FEAC channels are still enabled. This bit is ignored in the E3 mode.

0 = do not transmit DS3 idle signal

1 = transmit DS3 idle signal

Bits 6, 7: E3 National Bit Control (E3SnC[1:0]). These bits determine the source of the E3 National bit (Sn). On

the receive side, the Sn bit is always routed to the T3E3IR register as well as the HDLC controller and the FEAC

controller. These bits are ignored in DS3 mode.

E3SnC1

E3SnC0

SOURCE OF THE E3 NATIONAL BIT (Sn)

Force the Sn bit to logic 1

Source the Sn bit from the HDLC controller

Source the Sn bit from the FEAC controller

Force the Sn bit to logic 0

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