- 您现在的位置：买卖IC网 > PDF目录11560 > DS3148N (Maxim Integrated Products)IC 8CH DS3/3 FRAMER 349-BGA PDF资料下载
参数资料
| 型号： | DS3148N |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 71/89页 |
| 文件大小： | 0K |
| 描述： | IC 8CH DS3/3 FRAMER 349-BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 控制器类型： | DS3/E3 调帧器 |
| 接口： | LIU |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 640mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 349-BGA 裸露焊盘 |
| 供应商设备封装： | 349-HCBGA（27x27） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页当前第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
73 of 89
SAMPLE/PRELOAD. SAMPLE/PRELOAD is a mandatory instruction for the IEEE 1149.1 specification. This
instruction supports two functions. The digital I/Os of the device can be sampled at the boundary scan register
without interfering with the normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also
allows the device to shift data into the boundary scan register through JTDI using the Shift-DR state.
EXTEST. EXTEST allows testing of all interconnections to the device. When the EXTEST instruction is latched in
the instruction register, the following actions occur. Once enabled by the Update-IR state, the parallel outputs of all
digital output pins are driven. The boundary scan register is connected between JTDI and JTDO. The Capture-DR
samples all digital inputs into the boundary scan register.
BYPASS. When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the device’s normal
operation.
IDCODE. When the IDCODE instruction is latched into the parallel instruction register, the identification test
register is selected. The device identification code is loaded into the identification register on the rising edge of
JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially
through JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel
output.
HIGHZ. All digital outputs are placed into a high-impedance state. The bypass register is connected between JTDI
and JTDO.
CLAMP. All digital output pins output data from the boundary scan parallel output while connecting the bypass
register between JTDI and JTDO. The outputs do not change during the CLAMP instruction.
Table 9-B. JTAG ID Code
DEVICE
REVISION
DEVICE CODE
MANUFACTURER’S CODE
REQUIRED
DS3146
Consult factory
0000000000010101
00010100001
1
DS3148
Consult factory
0000000000010110
00010100001
1
DS31412
Consult factory
0000000000010111
00010100001
1
9.3 JTAG Scan Registers
IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An
optional test register, the identification register, has been included in the design and is used with the IDCODE
instruction and the Test-Logic-Reset state of the TAP controller.
Bypass Register
The bypass register is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions that
provides a short path between JTDI and JTDO.
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. The device
ID code always has a 1 in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and
number of continuation bytes, followed by 16 bits for the device and 4 bits for the version.
Boundary Scan Register
The boundary scan register contains a shift register path and a latched parallel output for all control cells and digital
I/O cells.
相关PDF资料 |
PDF描述 |
|---|---|
| VI-24K-IX-S | CONVERTER MOD DC/DC 40V 75W |
| PIC16C54C-20E/SO | IC MCU OTP 512X12 18SOIC |
| PIC16C54C-04E/SS | IC MCU OTP 512X12 20SSOP |
| PIC12C509T-04/SM | IC MCU OTP 1KX12 8-SOIJ |
| PIC12C508T-04I/SM | IC MCU OTP 512X12 8-SOIJ |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS315 | 制造商:Hubbell Wiring Device-Kellems 功能描述:SWITCH, DECO SER, 3W, 15A 120/277V, BR |
| DS3150 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:3.3V, DS3/E3/STS-1 Line Interface Unit |
| DS3150DK | 功能描述:网络开发工具 DS3150 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| DS3150G | 功能描述:IC LIU T3/E3/STS-1 49-BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件 |
| DS3150GN | 功能描述:IC LIU T3/E3/STS-1 IND 49-BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件 |
发布紧急采购，3分钟左右您将得到回复。