参数资料
型号: DS32512N#
厂商: Maxim Integrated Products
文件页数: 50/130页
文件大小: 0K
描述: IC LIU DS3/E3/STS-1 484-BGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
类型: 线路接口装置(LIU)
规程: DS3
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 484-BGA
供应商设备封装: 484-BGA(23x23)
包装: 管件
DS32506/DS32508/DS32512
26 of 130
8.2.9 Driver Monitor and Output Failure Detection
The transmit driver monitor compares the amplitude of the transmit waveform to thresholds VTXMIN and VTXMAX. If
the amplitude is less than VTXMIN or greater than VTXMAX for approximately 32 MCLK cycles, then the monitor
activates the TDM output pin (if the hardware interface is enabled) and sets the LIU.SR:TDM status bit. The setting
of LIU.SR:TDM can cause an interrupt if enabled by LIU.SRIE:TDMIE. When the transmitter is disabled, the
transmit driver monitor is also disabled. The transmit driver monitor is clocked by the LIU’s reference clock.
Note that the transmit driver monitor can be affected by reflections caused by shorts and opens on the line. A short
circuit at a distance less than a few inches (~11 inches for FR-4 material) can introduce inverted reflections that
reduce the outgoing pulse amplitude below the VTXMIN threshold and thereby activate the TDM pin and/or the TDM
status bit. Similarly an open circuit a similar distance away can introduce noninverted reflections that increase the
outgoing amplitude above the VTXMAX threshold and thereby activate the TDM pin and/or the TDM status bit. Shorts
and opens at larger distances away from TXP/TXN can also activate the TDM pin and/or the TDM status bit, but
this effect is data-pattern dependent.
If either TXP or TXN is not connected (open), shorted to VDD, or shorted to VSS, then a transmit failure alarm is
declared by setting the LIU.SR:TFAIL status bit. A change of state of the TFAIL status bit can cause an interrupt if
enabled by LIU.SRIE:TFAILIE. TFAIL is cleared when activity is detected on both TXP and TXN.
8.2.10 Power-Down
To minimize power consumption when the transmitter is not being used, the TPD pin (all ports) or the
PORT.CR1:TPD configuration bit (per port) can be asserted. When the transmitter is powered down, the TXP and
TXN pins are put in a high-impedance state and the transmit drivers are powered down.
8.2.11 Jitter Generation (Intrinsic)
The transmitter meets the jitter generation requirements of all applicable standards in Table 8-1, with or without the
jitter attenuator enabled. Generated jitter is measured with a jitter-free, 0ppm input clock.
Table 8-1. Jitter Generation
DS325xx JITTER
WITHOUT CLAD
WITH CLAD
SIGNAL STANDARD REQUIREMENT
BANDWIDTH
TYP
MAX
TYP
MAX
UNITS
DS3
GR-499
0.3 UIRMS
10Hz to 400kHz
0.01
0.02
0.01
0.02
UIRMS
DS3
T1.404
0.5 UIP-P
10Hz to 400kHz
0.02
0.03
0.05
0.06
UIP-P
DS3
T1.404
0.05 UIP-P
30kHz to 400kHz
0.015
0.025
0.04
0.05
UIP-P
E3
G.751
0.05 UIP-P
100Hz to 800kHz
0.02
0.03
0.04
0.05
UIP-P
STS-1
GR-253
0.01 UIRMS
12kHz to 400kHz
0.005
0.008
0.007
0.01
UIRMS
STS-1
GR-253
0.10 UIP-P
12kHz to 400kHz
0.04
0.06
0.08
UIP-P
8.2.12 Jitter Transfer
Without the jitter attenuator on the transmit side, the transmitter passes jitter through unchanged. With the jitter
attenuator enabled on the transmit side, the transmitter meets the jitter transfer requirements of all applicable
telecommunication standards in Table 1-1. See Figure 8-7.
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