参数资料
| 型号： | DS32512N# |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 56/130页 |
| 文件大小： | 0K |
| 描述： | IC LIU DS3/E3/STS-1 484-BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 60 |
| 类型： | 线路接口装置（LIU） |
| 规程： | DS3 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 484-BGA |
| 供应商设备封装： | 484-BGA（23x23） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页当前第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页
DS32506/DS32508/DS32512
31 of 130
(AT&T 734A or equivalent). The AGC and the equalizer work simultaneously but independently to supply a signal
of nominal amplitude and pulse shape to the clock and data recovery block. The AGC/equalizer block automatically
handles direct (0 meters) monitoring of the transmitter output signal. The real-time receiver gain level can be read
from the LIU.RGLR register. Note: When the receiver preamp is on (LIU.SR:RPAS = 1), the actual receiver gain
level is the level read from the LIU.RGLR register plus 14dB.
8.3.4 Clock and Data Recovery (CDR)
The CDR block takes the amplified, equalized signal from the AGC/equalizer block and produces separate clock,
positive data, and negative data signals. The CDR operates from the LIU’s reference clock. See Section 8.7.1 for
more information about reference clocks and clock selection.
The receiver locks onto the incoming signal using a clock recovery PLL. The PLL lock status is indicated in the
LIU.SR:RLOL status bit. The RLOL bit is set when the difference between recovered clock frequency and reference
clock frequency is greater than 7900ppm and cleared when the difference is less than 7700ppm. A change of state
of the RLOL status bit can cause an interrupt if enabled by LIU.SRIE:RLOLIE. Note that if the reference clock is not
present, RLOL is not set.
8.3.5 Loss-of-Signal (LOS) Detector
The receiver contains analog and digital LOS detectors. The analog LOS (ALOS) detector resides in the
AGC/equalizer block. At approximately 23dB below nominal pulse amplitude ALOS is declared by setting the
LIU.SR:ALOS status bit. A change of state of the ALOS status bit can cause an interrupt if enabled by
LIU.SRIE:ALOSIE. When ALOS is declared the CDR block forces all zeros out of the data recovery circuit, causing
digital LOS (DLOS), which is indicated by the RLOS pin and the LINE.RSR:LOS status bit. During ALOS the RCLK
pin follows the LIU’s reference clock, since no clock information is being received on RXP/RXN. ALOS is cleared at
approximately 22dB below nominal pulse amplitude. When the preamp is enabled (Section 8.3.2) ALOS is declared
at approximately 37dB below nominal and cleared at approximately 36dB below nominal.
The digital LOS detector declares DLOS when it detects 192 consecutive zeros in the recovered data stream.
When DLOS occurs, the receiver asserts the RLOS pin (if the hardware interface is enabled) and the
LINE.RSR:LOS status bit. DLOS is cleared when there are no EXZ occurrences over a span of 192 clock periods.
An EXZ occurrence is defined as three or more consecutive zeros in DS3 and STS-1 modes and four or more
consecutive zeros in E3 mode. The RLOS pin and the LOS status bit are deasserted when the DLOS condition is
cleared. A change of state of the LINE.RSR:LOS status bit can cause an interrupt if enabled by
LINE.RSRIE:LOSIE. DLOS is only declared when B3ZS/HDB3 decoding is enabled (LINE.RCR:RZSD = 0). When
B3ZS/HDB3 decoding is disabled in the LIU, decoding should be enabled in the neighboring DS3/E3 framer, and
DLOS should be detected and report by the framer.
The requirements of ANSI T1.231 and ITU-T G.775 for DS3 LOS defects are met by the DLOS detector, which
asserts RLOS when it counts 192 consecutive zeros coming out of the CDR block and clears RLOS when it counts
192 consecutive pulse intervals without excessive zero occurrences.
The requirements of ITU-T G.775 for E3 LOS defects are met by a combination of the ALOS detector and the
DLOS detector, as follows:
For E3 RLOS Assertion:
1) The ALOS detector in the AGC/equalizer block detects that the incoming signal is less than or
equal to a signal level approximately 23dB below nominal, and mutes the data coming out of
the clock and data recovery block. (23dB below nominal is in the “tolerance range” of G.775,
where LOS may or may not be declared.)
2) The DLOS detector counts 192 consecutive zeros coming out of the CDR block and asserts
RLOS. (192 meets the 10
≤ N ≤ 255 pulse-interval duration requirement of G.775.)
For E3 RLOS Clear:
1) The ALOS detector in the AGC/equalizer block detects that the incoming signal is greater than
or equal to a signal level approximately 22dB below nominal, and enables data to come out of
the CDR block. (22dB is in the “tolerance range” of G.775, where LOS may or may not be
declared.)
2) The DLOS detector counts 192 consecutive pulse intervals without EXZ occurrences and
deasserts RLOS. (192 meets the 10
≤ N ≤ 255 pulse-interval duration requirement of G.775.)
相关PDF资料 |
PDF描述 |
|---|---|
| MAX1228AEEP+T | IC ADC 12BIT 300KSPS 20-QSOP |
| VI-26W-IU-F4 | CONVERTER MOD DC/DC 5.5V 200W |
| DS32512+ | IC LIU DS3/E3/STS-1 484-BGA |
| VI-26W-IU-F2 | CONVERTER MOD DC/DC 5.5V 200W |
| M83723/71W1020Y | CONN RCPT 2POS WALL MT W/SCKT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS32512N# | 功能描述:网络控制器与处理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS32512N+ | 功能描述:网络控制器与处理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS32512NA2 | 制造商:Maxim Integrated Products 功能描述:DS32512 X12 DS3/E3 LIU REVA2 IND - Rail/Tube |
| DS32512NW | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS32512W | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
发布紧急采购，3分钟左右您将得到回复。