- 您现在的位置：买卖IC网 > PDF目录1917 > DSPB56364AF100 (Freescale Semiconductor)IC DSP 24BIT AUD 100MHZ 100-LQFP PDF资料下载
参数资料
| 型号： | DSPB56364AF100 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 13/148页 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT AUD 100MHZ 100-LQFP |
| 标准包装： | 90 |
| 系列： | DSP56K/Symphony |
| 类型： | 音频处理器 |
| 接口： | 主机接口，I²C，SAI，SPI |
| 时钟速率： | 100MHz |
| 非易失内存： | ROM（24 kB） |
| 芯片上RAM： | 11.25kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 3.30V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-LQFP（14x14） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页
Serial Host Interface
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor
2-7
2.7
Serial Host Interface
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode.
Table 2-9 Serial Host Interface Signals
Signal
Name
Signal
Type
State During
Reset
Signal Description
SCK
Input or
output
Tri-stated
SPI Serial Clock—The SCK signal is an output when the SPI is configured as a master
and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is
configured as a master, the SCK signal is derived from the internal SHI clock generator.
When the SPI is configured as a slave, the SCK signal is an input, and the clock signal
from the external master synchronizes the data transfer. The SCK signal is ignored by
the SPI if it is defined as a slave and the slave select (SS) signal is not asserted. In both
the master and slave SPI devices, data is shifted on one edge of the SCK signal and is
sampled on the opposite edge where data is stable. Edge polarity is determined by the
SPI transfer protocol.
SCL
Input or
output
Tri-stated
I2C Serial Clock—SCL carries the clock for I2C bus transactions in the I2C mode. SCL
is a Schmitt-trigger input when configured as a slave and an open-drain output when
configured as a master. SCL should be connected to VCC through a pull-up resistor.
This signal is tri-stated during hardware, software, and individual reset. Thus, there is
no need for an external pull-up in this state.
This input is 5 V tolerant.
MISO
Input or
output
Tri-stated
SPI Master-In-Slave-Out—When the SPI is configured as a master, MISO is the
master data input line. The MISO signal is used in conjunction with the MOSI signal for
transmitting and receiving serial data. This signal is a Schmitt-trigger input when
configured for the SPI Master mode, an output when configured for the SPI Slave
mode, and tri-stated if configured for the SPI Slave mode when SS is deasserted. An
external pull-up resistor is not required for SPI operation.
SDA
Input or
open-drain
output
Tri-stated
I2C Data and Acknowledge—In I2C mode, SDA is a Schmitt-trigger input when
receiving and an open-drain output when transmitting. SDA should be connected to
VCC through a pull-up resistor. SDA carries the data for I
2C transactions. The data in
SDA must be stable during the high period of SCL. The data in SDA is only allowed to
change when SCL is low. When the bus is free, SDA is high. The SDA line is only
allowed to change during the time SCL is high in the case of start and stop events. A
high-to-low transition of the SDA line while SCL is high is a unique situation, and is
defined as the start event. A low-to-high transition of SDA while SCL is high is a unique
situation defined as the stop event.
This signal is tri-stated during hardware, software, and individual reset. Thus, there is
no need for an external pull-up in this state.
This input is 5 V tolerant.
MOSI
Input or
output
Tri-stated
SPI Master-Out-Slave-In—When the SPI is configured as a master, MOSI is the
master data output line. The MOSI signal is used in conjunction with the MISO signal
for transmitting and receiving serial data. MOSI is the slave data input line when the
SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for
the SPI Slave mode.
相关PDF资料 |
PDF描述 |
|---|---|
| DSPB56366AG120 | IC DSP 24BIT AUD 120MHZ 144-LQFP |
| DSPB56367AG150 | IC DSP 24BIT 150MHZ 144-LQFP |
| DSPB56371AF180 | IC DSP 24BIT 180MHZ 80-LQFP |
| DSPB56374AEC | IC DSP 24BIT 150MHZ 52-LQFP |
| DSPB56720CAG | DSP 24BIT AUD 200MHZ 144-LQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DSPB56364FU100 | 制造商:Rochester Electronics LLC 功能描述:24 BIT AUDIO DSP - Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| DSPB56364FU100R2 | 制造商:Freescale Semiconductor 功能描述:DSP FIX PT 24BIT 100MHZ 100MIPS 100LQFP - Tape and Reel |
| DSPB56366AG120 | 功能描述:数字信号处理器和控制器 - DSP, DSC LEAD FREE DSPB56366 RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSPB56366PV120 | 制造商:Motorola Inc 功能描述: 制造商:Freescale Semiconductor 功能描述:IC 制造商:MOTOROLA 功能描述: |
| DSPB56367AG150 | 功能描述:数字信号处理器和控制器 - DSP, DSC 150Mhz/150MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
发布紧急采购，3分钟左右您将得到回复。