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| 型号： | DSPB56367AG150 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 10/100页 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT 150MHZ 144-LQFP |
| 标准包装： | 60 |
| 系列： | DSP56K/Symphony |
| 类型： | 音频处理器 |
| 接口： | 主机接口，I²C，SAI，SPI |
| 时钟速率： | 150MHz |
| 非易失内存： | ROM（240 kB） |
| 芯片上RAM： | 69kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.80V |
| 工作温度： | -40°C ~ 95°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
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Enhanced Serial Audio Interface
DSP56367 Technical Data, Rev. 2.1
Freescale Semiconductor
2-13
2.12
Enhanced Serial Audio Interface
Table 2-11 Enhanced Serial Audio Interface Signals
Signal
Name
Signal Type
State during
Reset
Signal Description
HCKR
PC2
Input or Output
Input, Output, or
Disconnected
GPIO
Disconnected
High Frequency Clock for Receiver—When programmed as an input, this
signal provides a high frequency clock source for the ESAI receiver as an
alternate to the DSP core clock. When programmed as an output, this signal
can serve as a high-frequency sample clock (e.g., for external digital to analog
converters [DACs]) or as an additional system clock.
Port C 2—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 3.3V tolerant.
HCKT
PC5
Input or Output
Input, Output, or
Disconnected
GPIO
Disconnected
High Frequency Clock for Transmitter—When programmed as an input,
this signal provides a high frequency clock source for the ESAI transmitter as
an alternate to the DSP core clock. When programmed as an output, this
signal can serve as a high frequency sample clock (e.g., for external DACs)
or as an additional system clock.
Port C 5—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 3.3V tolerant.
FSR
PC1
Input or Output
Input, Output, or
Disconnected
GPIO
Disconnected
Frame Sync for Receiver—This is the receiver frame sync input/output
signal. In the asynchronous mode (SYN=0), the FSR pin operates as the
frame sync input or output used by all the enabled receivers. In the
synchronous mode (SYN=1), it operates as either the serial flag 1 pin
(TEBE=0), or as the transmitter external buffer enable control (TEBE=1,
RFSD=1).
When this pin is configured as serial flag pin, its direction is determined by the
RFSD bit in the RCCR register. When configured as the output flag OF1, this
pin will reflect the value of the OF1 bit in the SAICR register, and the data in
the OF1 bit will show up at the pin synchronized to the frame sync in normal
mode or the slot in network mode. When configured as the input flag IF1, the
data value at the pin will be stored in the IF1 bit in the SAISR register,
synchronized by the frame sync in normal mode or the slot in network mode.
Port C 1—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 3.3V tolerant.
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