- 您现在的位置：买卖IC网 > PDF目录1917 > DSPB56367AG150 (Freescale Semiconductor)IC DSP 24BIT 150MHZ 144-LQFP PDF资料下载
参数资料
| 型号： | DSPB56367AG150 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 90/100页 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT 150MHZ 144-LQFP |
| 标准包装： | 60 |
| 系列： | DSP56K/Symphony |
| 类型： | 音频处理器 |
| 接口： | 主机接口，I²C，SAI，SPI |
| 时钟速率： | 150MHz |
| 非易失内存： | ROM（240 kB） |
| 芯片上RAM： | 69kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.80V |
| 工作温度： | -40°C ~ 95°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页当前第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页
External Data Bus
DSP56367 Technical Data, Rev. 2.1
Freescale Semiconductor
2-5
2.7
External Data Bus
2.8
External Bus Control
Table 2-6 External Data Bus Signals
Signal Name
Type
State during
Reset
Signal Description
D0–D23
Input/Output
Tri-Stated
Data Bus—When the DSP is the bus master, D0–D23 are active-high,
bidirectional input/outputs that provide the bidirectional data bus for external
program and data memory accesses. Otherwise, D0–D23 are tri-stated.
Table 2-7 External Bus Control Signals
Signal Name
Type
State During
Reset
Signal Description
AA0–AA2/
RAS0–RAS2
Output
Tri-Stated
Address Attribute or Row Address Strobe—When defined as AA, these signals can
be used as chip selects or additional address lines. When defined as RAS, these
signals can be used as RAS for DRAM interface. These signals are tri-statable outputs
with programmable polarity.
CAS
Output
Tri-Stated
Column Address Strobe— When the DSP is the bus master, CAS is an active-low
output used by DRAM to strobe the column address. Otherwise, if the bus mastership
enable (BME) bit in the DRAM control register is cleared, the signal is tri-stated.
RD
Output
Tri-Stated
Read Enable—When the DSP is the bus master, RD is an active-low output that is
asserted to read external memory on the data bus (D0-D23). Otherwise, RD is tri-stated.
WR
Output
Tri-Stated
Write Enable—When the DSP is the bus master, WR is an active-low output that is
asserted to write external memory on the data bus (D0-D23). Otherwise, WR is tri-stated.
TA
Input
Ignored Input Transfer Acknowledge—If the DSP is the bus master and there is no external bus
activity, or the DSP is not the bus master, the TA input is ignored. The TA input is a data
transfer acknowledge (DTACK) function that can extend an external bus cycle
indefinitely. Any number of wait states (1, 2. . .infinity) may be added to the wait states
inserted by the BCR by keeping TA deasserted. In typical operation, TA is deasserted
at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is
deasserted before the next bus cycle. The current bus cycle completes one clock
period after TA is asserted synchronous to the internal system clock. The number of
wait states is determined by the TA input or by the bus control register (BCR),
whichever is longer. The BCR can be used to set the minimum number of wait states
in external bus cycles.
In order to use the TA functionality, the BCR must be programmed to at least one wait
state. A zero wait state access cannot be extended by TA deassertion, otherwise
improper operation may result. TA can operate synchronously or asynchronously,
depending on the setting of the TAS bit in the operating mode register (OMR).
TA functionality may not be used while performing DRAM type accesses, otherwise
improper operation may result.
相关PDF资料 |
PDF描述 |
|---|---|
| DSPB56371AF180 | IC DSP 24BIT 180MHZ 80-LQFP |
| DSPB56374AEC | IC DSP 24BIT 150MHZ 52-LQFP |
| DSPB56720CAG | DSP 24BIT AUD 200MHZ 144-LQFP |
| DSPB56724AG | DSP 24BIT AUD 250MHZ 144-LQFP |
| DSPIC30F2010T-20E/MM | IC DSPIC MCU/DSP 12K 28QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DSPB56367PV150 | 功能描述:数字信号处理器和控制器 - DSP, DSC 150Mhz/ 150MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSPB5636AG120 | 制造商:Freescale Semiconductor 功能描述: |
| DSPB56371AF150 | 功能描述:数字信号处理器和控制器 - DSP, DSC 150 MHZ VERSION DSPB371 RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSPB56371AF180 | 功能描述:数字信号处理器和控制器 - DSP, DSC BLANK ROM VERSION 56371 RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSPB56371AF180 | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor (DSP) IC |
发布紧急采购，3分钟左右您将得到回复。