- 您现在的位置：买卖IC网 > PDF目录1917 > DSPB56367AG150 (Freescale Semiconductor)IC DSP 24BIT 150MHZ 144-LQFP PDF资料下载
参数资料
| 型号： | DSPB56367AG150 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 2/100页 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT 150MHZ 144-LQFP |
| 标准包装： | 60 |
| 系列： | DSP56K/Symphony |
| 类型： | 音频处理器 |
| 接口： | 主机接口，I²C，SAI，SPI |
| 时钟速率： | 150MHz |
| 非易失内存： | ROM（240 kB） |
| 芯片上RAM： | 69kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.80V |
| 工作温度： | -40°C ~ 95°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
第1页当前第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页
Interrupt and Mode Control
DSP56367 Technical Data, Rev. 2.1
2-6
Freescale Semiconductor
2.9
Interrupt and Mode Control
The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.
After RESET is deasserted, these inputs are hardware interrupt request lines.
BR
Output
(deasserted)
Bus Request—BR is an active-low output, never tri-stated. BR is asserted when the
DSP requests bus mastership. BR is deasserted when the DSP no longer needs the
bus. BR may be asserted or deasserted independent of whether the DSP56367 is a
bus master or a bus slave. Bus “parking” allows BR to be deasserted even though the
DSP56367 is the bus master. (See the description of bus “parking” in the BB signal
description.) The bus request hold (BRH) bit in the BCR allows BR to be asserted under
software control even though the DSP does not need the bus. BR is typically sent to an
external bus arbitrator that controls the priority, parking, and tenure of each master on
the same external bus. BR is only affected by DSP requests for the external bus, never
for the internal bus. During hardware reset, BR is deasserted and the arbitration is reset
to the bus slave state.
BG
Input
Ignored Input Bus Grant—BG is an active-low input. BG is asserted by an external bus arbitration
circuit when the DSP56367 becomes the next bus master. When BG is asserted, the
DSP56367 must wait until BB is deasserted before taking bus mastership. When BG is
deasserted, bus mastership is typically given up at the end of the current bus cycle.
This may occur in the middle of an instruction that requires more than one external bus
cycle for execution.
For proper BG operation, the asynchronous bus arbitration enable bit (ABE) in the
OMR register must be set.
BB
Input/
Output
Input
Bus Busy—BB is a bidirectional active-low input/output. BB indicates that the bus is
active. Only after BB is deasserted can the pending bus master become the bus master
(and then assert the signal again). The bus master may keep BB asserted after ceasing
bus activity regardless of whether BR is asserted or deasserted. This is called “bus
parking” and allows the current bus master to reuse the bus without rearbitration until
another device requires the bus. The deassertion of BB is done by an “active pull-up”
method (i.e., BB is driven high and then released and held high by an external pull-up
resistor).
For proper BB operation, the asynchronous bus arbitration enable bit (ABE) in the OMR
register must be set.
BB requires an external pull-up resistor.
Table 2-7 External Bus Control Signals (continued)
Signal Name
Type
State During
Reset
Signal Description
相关PDF资料 |
PDF描述 |
|---|---|
| DSPB56371AF180 | IC DSP 24BIT 180MHZ 80-LQFP |
| DSPB56374AEC | IC DSP 24BIT 150MHZ 52-LQFP |
| DSPB56720CAG | DSP 24BIT AUD 200MHZ 144-LQFP |
| DSPB56724AG | DSP 24BIT AUD 250MHZ 144-LQFP |
| DSPIC30F2010T-20E/MM | IC DSPIC MCU/DSP 12K 28QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DSPB56367PV150 | 功能描述:数字信号处理器和控制器 - DSP, DSC 150Mhz/ 150MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSPB5636AG120 | 制造商:Freescale Semiconductor 功能描述: |
| DSPB56371AF150 | 功能描述:数字信号处理器和控制器 - DSP, DSC 150 MHZ VERSION DSPB371 RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSPB56371AF180 | 功能描述:数字信号处理器和控制器 - DSP, DSC BLANK ROM VERSION 56371 RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSPB56371AF180 | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor (DSP) IC |
发布紧急采购，3分钟左右您将得到回复。