- 您现在的位置：买卖IC网 > PDF目录15530 > EVAL-ADUC7039QSPZ (Analog Devices Inc)BOARD EVAL FOR ADUC7039 PDF资料下载
参数资料
| 型号： | EVAL-ADUC7039QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 28/92页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADUC7039 |
| 设计资源： | ADuC7039QSPZ Gerber Files EVAL-ADuC7039 Schematic & Brd Outline |
| 标准包装： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 类型： | MCU |
| 适用于相关产品： | ADuC7039 |
| 所含物品： | 板 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页当前第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页
ADuC7039
Data Sheet
Rev. D | Page 34 of 92
ADC MMR INTERFACE
The ADC is controlled and configured through a number of
MMRs that are described in detail in the following sections.
All bits defined in the top eight MSBs (Bits[15:8]) of the ADCSTA
MMR are used as flags only and do not generate interrupts. All
bits defined in the lower eight LSBs (Bits[7:0]) of this MMR are
logic OR’ed to produce a single ADC interrupt to the MCU core. In
response to an ADC interrupt, user code should interrogate the
ADCSTA MMR to determine the source of the interrupt. Each
ADC interrupt source can be individually masked via the
ADCMSKI MMR described in the ADC Interrupt Mask
Register section.
All ADC result ready bits are cleared by a read of the ADC0DAT
MMR. If the current channel ADC is not enabled, all ADC result
ready bits are cleared by a read of the ADC1DAT MMR. To
ensure that I-ADC and V/T-ADC conversion data are syn-
chronous, user code should first read the ADC1DAT MMR
and then ADC0DAT MMR. New ADC conversion results are
not written to the ADCxDAT MMRs unless the respective ADC
result ready bits are first cleared. The only exception to this rule
is when the ARM core is powered down and the ADC subsystem
is active. In this mode, ADCxDAT registers always contain the
most recent ADC conversion result even though the ready bits
have not been cleared.
ADC Status Register
Name:
ADCSTA
Address:
0xFFFF0500
Default Value: 0x0000
Access:
Read only
Function:
This read-only register holds general status
information related to the mode of operation
or current status of the ADCs.
Table 27. ADCSTA MMR Bit Designations
Bit
Description
15
ADC calibration status.
This bit is set automatically in hardware to indicate an ADC calibration cycle has been completed.
This bit is cleared automatically after any of the following registers are written to: ADCMDE, ADCFLT, or ADC0CON.
14
Reserved.
13
ADC voltage/temperature conversion error.
This bit is set automatically in hardware to indicate that a voltage conversion overrange or underrange has occurred. The
conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case.
This bit is cleared automatically when a valid (in-range) voltage conversion result is written to the ADC1DAT register.
12
ADC current conversion error.
This bit is set automatically in hardware to indicate that a current conversion overrange or underrange has occurred. The
conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case.
This bit is cleared automatically when a valid (in-range) current conversion result is written to the ADC0DAT register.
11 to 6
Not used. These bits are reserved for future functionality and should not be monitored by user code.
5
ADC continuous interrupt bit.
This bit is set automatically after each I-ADC conversion. Results of the ADCs might not be valid. This bit is only active if enabled in
the ADCMDE MMR.
This bit is cleared when user code reads ADC0DAT.
4
Current channel ADC comparator threshold.
This bit is only valid if the current channel ADC comparator is enabled via the ADCCFG MMR.
This bit is set by hardware if the absolute value of the I-ADC conversion result exceeds the value written in the ADC0TH MMR.
This bit is cleared automatically by hardware when reconfiguring the ADC.
3
Reserved.
2
Temperature conversion result ready bit.
If the temperature channel ADC is enabled, this bit is set by hardware as soon as a valid temperature conversion result is written in
the temperature data register (ADC1DAT MMR). It is also set at the end of a calibration.
This bit is cleared when user code reads either ADC1DAT or ADC0DAT.
1
Voltage conversion result ready bit.
If the voltage channel ADC is enabled, this bit is set by hardware as soon as a valid voltage conversion result is written in the
voltage data register (ADC1DAT MMR). It is also set at the end of a calibration.
This bit is cleared when user code reads either ADC1DAT or ADC0DAT.
0
Current conversion result ready bit.
If the current channel ADC is enabled, this bit is set by hardware as soon as a valid current conversion result is written in the
current data register (ADC0DAT MMR). It is also set at the end of a calibration.
This bit is cleared when user code reads ADC0DAT.
相关PDF资料 |
PDF描述 |
|---|---|
| EYM15DRSH | CONN EDGECARD 30POS DIP .156 SLD |
| AIUR-06-102K | INDUCTOR POWER 1000UH 10% T/H |
| V300C3V3C50B2 | CONVERTER MOD DC/DC 3.3V 50W |
| EGM15DRSH | CONN EDGECARD 30POS DIP .156 SLD |
| EVAL-ADUC7023QSPZ1 | BOARD EVAL FOR ADUC7023 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EVAL-ADUC7060QSPZ | 功能描述:KIT DEV QUICK START ADUC7060 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ PLUS 套件 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| EVAL-ADUC7060QSPZU1 | 制造商:Analog Devices 功能描述: |
| EVALADUC7060QSPZU2 | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Boxed Product (Development Kits) |
| EVAL-ADUC7061MKZ | 功能描述:开发板和工具包 - ARM Quick Start Development System RoHS:否 制造商:Arduino 产品:Development Boards 工具用于评估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口类型:DAC, ICSP, JTAG, UART, USB 工作电源电压:3.3 V |
| EVAL-ADUC7061MKZ | 制造商:Analog Devices 功能描述:ADUC7061MKZ EvaluationBoard |
发布紧急采购，3分钟左右您将得到回复。