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| 型号： | EVAL-ADUC7039QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 74/92页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADUC7039 |
| 设计资源： | ADuC7039QSPZ Gerber Files EVAL-ADuC7039 Schematic & Brd Outline |
| 标准包装： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 类型： | MCU |
| 适用于相关产品： | ADuC7039 |
| 所含物品： | 板 |
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ADuC7039
Data Sheet
Rev. D | Page 76 of 92
SPI Control Register
Name:
SPICON
Address:
0xFFFF0A10
Default Value:
0x0000
Access:
Read/write
Function:
This 16-bit MMR configures the SPI peripheral in both master and slave modes.
Table 55. SPICON MMR Bit Designations
Bit
Description
15 to 14
SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer.
00 = Tx interrupt occurs when 1 byte has been transferred. Rx interrupt occurs when 1 or more bytes have been received into the FIFO.
01 = Tx interrupt occurs when 2 bytes have been transferred. Rx interrupt occurs when 1 or more bytes have been received into
the FIFO.
10 = Tx interrupt occurs when 3 bytes have been transferred. Rx interrupt occurs when 3 or more bytes have been received into
the FIFO.
11 = Tx interrupt occurs when 4 bytes have been transferred. Rx interrupt occurs when the Rx FIFO is full, or 4 bytes are present.
13
SPI Tx FIFO flush enable bit.
Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then
either the last transmitted value or 0x00 is transmitted depending on SPICON[7]. Any writes to the Tx FIFO are ignored while this
bit is set.
Clear this bit to disable Tx FIFO flushing.
12
SPI Rx FIFO flush enable bit.
Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is set,
all incoming data is ignored and no interrupts are generated. If set and SPICON[6] = 0, a read of the Rx FIFO initiates a transfer.
Clear this bit to disable Rx FIFO flushing.
11
Continuous transfer enable.
This bit is set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in
the SPITX register. SS is asserted and remains asserted for the duration of each 8-bit serial transfer until TX is empty.
This bit is cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data
exists in the SPITX register, then a new transfer is initiated after a stall period of 1 serial clock cycle.
10
Loop back enable bit.
This bit is set by the user to connect MISO to MOSI and test software.
This bit is cleared by the user to be in normal mode.
9
Slave MISO output enable bit.
Set this bit to disable the output driver on the MISO pin. The MISO pin becomes open drain when this bit is set.
Clear this bit for MISO to operate as normal.
8
SPIRX overflow overwrite enable.
This bit is set by the user; the valid data in the SPIRX register is overwritten by the new serial byte received.
This bit is cleared by the user; the new serial byte received is discarded.
7
SPI transmit zeros when Tx FIFO enable bit.
Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO.
Clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO.
6
SPI transfer and interrupt mode.
This bit is set by the user to initiate a transfer with a write to the SPITX register. Interrupt only occurs when SPITX is empty.
This bit is cleared by the user to initiate a transfer with a read of the SPIRX register. Interrupt only occurs when SPIRX is full.
5
LSB first transfer enable bit.
This bit is set by the user; the LSB is transmitted first.
This bit is cleared by the user; the MSB is transmitted first.
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