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| 型号： | EVAL-ADUC7039QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 39/92页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADUC7039 |
| 设计资源： | ADuC7039QSPZ Gerber Files EVAL-ADuC7039 Schematic & Brd Outline |
| 标准包装： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 类型： | MCU |
| 适用于相关产品： | ADuC7039 |
| 所含物品： | 板 |
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ADuC7039
Data Sheet
Rev. D | Page 44 of 92
In ADC low power mode, the ADC, Σ-Δ modulator clock is
no longer driven at 512 kHz but is driven directly from the
on-chip low power (128 kHz) oscillator. Subsequently, for the
same ADCFLT configurations in normal mode, all filter values
should be scaled by a factor of approximately four.
In general, it is possible to program different values of SF and
AF in the ADCFLT register and achieve the same ADC update
rate. In practical terms, the trade off with any value of ADCFLT
is frequency response vs. ADC noise. For optimum filter response
and ADC noise when using combinations of SF and AF, best
practice suggests choosing an SF in the range of 16 decimal to
40 decimal, or 0x10 to 0x28, and then increasing the AF value
to achieve the required ADC throughput. Table 35 shows some
common ADCFLT configurations.
ADC MODES OF OPERATION
The ADCs can be configured into reduced (low power) or
full power (normal) mode of operation by configuring
ADCMDE[3] as appropriate. The ARM7 MCU can also be
configured in low power modes of operation (POWCON[5:3]).
The core power modes are independently controlled and are
not related to the ADC power modes described in this section.
ADC Normal Power Mode
In normal mode, the current and voltage/temperature channels
are fully enabled. The ADC modulator clock is 512 kHz and
enables the ADCs to provide regular conversion results at a
rate of between 10 Hz and 1 kHz (see the ADC Filter Register
section). Both channels are under full control of the MCU and
can be reconfigured at any time. The default ADC update rate
for all channels in this mode is 1.0 kHz.
It is worth emphasizing that I-ADC and V/T-ADC channels can
be configured to initiate periodic, normal power mode, high
accuracy, single conversion cycles before returning to ADC full
power-down mode. This flexibility is facilitated under full MCU
control via the ADCMDE MMR; it ensures that continuous peri-
odic monitoring of battery current, voltage, and temperature
settings is feasible while ensuring the average dc current
consumption is minimized.
In ADC normal mode, the PLL must not be powered down.
ADC Low Power Mode
In ADC low power mode, the I-ADC is enabled in a reduced
power and reduced accuracy configuration. The ADC modu-
lator clock is now driven directly from the on-chip 128 kHz low
power oscillator. The gain of the ADC in this mode is fixed at 512.
All of the ADC peripheral functions (result counter, digital
comparator and accumulator) can be enabled in low power mode.
Typically, in low power mode, the I-ADC only, is configured
to run at a low update rate, continuously monitoring battery
current. The MCU is in power-down mode and wakes up when
the I-ADC interrupts the MCU. This happens after the I-ADC
detects a current conversion beyond a preprogrammed thre-
shold, setpoint, or a set number of conversions.
ADC Comparator and Accumulator
Every I-ADC result can also be compared to a preset threshold
level (ADC0TH) as configured via ADCCFG[3]. An MCU
interrupt is generated if the absolute (sign independent) value
of the ADC result is greater than the preprogrammed com-
parator threshold level.
Finally, a 32-bit accumulator (ADC0ACC) function can be
configured (ADCCFG[5]) allowing the I-ADC to add (or
subtract) multiple I-ADC sample results. User code can read
the accumulated value directly (ADC0ACC) without any
further software processing.
ADC Continuous Interrupt Mode
Setting ADCMDE[5] allows the user to generate an ADC
interrupt after each ADC conversion period, even if the ADC
filter is not fully settled. The corresponding ADC interrupt bit
in the ADCMSKI must also be set to allow the continuous
interrupt. In this mode of operation, ADCSTA[2:0] are used
as valid flags and should not be used to generate interrupts.
Table 35. Common ADCFLT Configurations
ADC Mode
SF
AF
Other Config.
ADCFLT
fADC
tSETTLE
Normal
0x1F
0x16
Chop on
0x961F
10 Hz
0.2 sec
Normal
0x07
0x00
None
0x0007
1 kHz
3 ms
Normal
0x07
0x00
Sinc3 modify
0x0087
1 kHz
3 ms
Low Power
0x10
0x03
Chop on
0x8310
20 Hz
100 ms
Low Power
0x10
0x09
Chop on
0x8910
10 Hz
200 ms
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| EVAL-ADUC7060QSPZU1 | 制造商:Analog Devices 功能描述: |
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