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| 型号： | EVAL-ADUC7039QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 38/92页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADUC7039 |
| 设计资源： | ADuC7039QSPZ Gerber Files EVAL-ADuC7039 Schematic & Brd Outline |
| 标准包装： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 类型： | MCU |
| 适用于相关产品： | ADuC7039 |
| 所含物品： | 板 |
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Data Sheet
ADuC7039
Rev. D | Page 43 of 92
ADC SINC3 DIGITAL FILTER RESPONSE
The overall frequency response on all ADuC7039 ADCs is
dominated by the low-pass filter response of the on-chip sinc3
digital filters. The sinc3 filters are used to decimate the ADC
Σ-Δ modulator output data bit stream to generate a valid 16-bit
data result. The digital filter response is identical for both ADCs
and is configured via the 16-bit ADC filter (ADCFLT) register.
This register determines the overall throughput rate of the
ADCs. The noise resolution of the ADCs is determined by the
programmed ADC throughput rate. In the case of the current
channel ADC, the noise resolution is determined by throughput
rate and selected gain.
The overall frequency response and the ADC throughput is
dominated by the configuration of the sinc3 filter decimation
factor (SF) bits (ADCFLT[6:0]) and the averaging factor (AF)
bits (ADCFLT[13:8]). Due to limitations on the digital filter
internal data path, there are some limitations on the allowable
combinations of SF and AF that can be used to generate a
required ADC output rate. This restriction limits the minimum
ADC update in normal power mode to 10 Hz. The calculation
of the ADC throughput rate is detailed in the ADCFLT bit
designations table and the restrictions on allowable combi-
nations of AF and SF values are outlined in Table 33.
By default, the ADCFLT = 0x0007 configures the ADCs for a
throughput of 1.0 kHz with all other filtering options (chop,
running average, averaging factor, and sinc3 modify) disabled.
A typical filter response based on this default configuration is
shown in Figure 14.
Figure 14. Typical Digital Filter Response at fADC = 1.0 kHz
(ADCFLT = 0x0007)
An additional sinc3 modify bit (ADCFLT[7]) is also available in
the ADCFLT register. This bit is set by user code to modify the
standard sinc3 frequency response increasing the filter stop-
band rejection by approximately 5 dB. This is achieved by
inserting a second notch (NOTCH2) at
fNOTCH2 = 1.333 × fNOTCH
where fNOTCH is the location of the first notch in the response.
There is a slight increase in ADC noise if this bit is active.
Figure 15 shows the modified 1 kHz filter response when the
sinc3 modify bit is active. The new notch is clearly visible at
1.33 kHz, as is the improvement in stop-band rejection when
compared to the standard 1 kHz response.
Figure 15. Modified Sinc3 Digital Filter Response at fADC = 1.0 kHz
(ADCFLT = 0x0087)
At very low throughput rates, the chop bit in the ADCFLT
register can be enabled to minimize offset errors and, more
importantly, temperature drift in the ADC offset error.
There are two primary variables (sinc3 decimation factor
and averaging factor) available to allow the user to select an
optimum filter response, trading off filter bandwidth against
ADC noise.
For example, with the chop bit (ADCFLT[15]) set to 1,
increasing the SF value (ADCFLT[6:0]) to 0x1F (31
decimal) and selecting an AF value (ADCFLT[13:8]) of
0x16 (22 decimal) results in an ADC throughput of 10 Hz.
The frequency response in this case is shown in Figure 16.
Figure 16. Typical Digital Filter Response at fADC = 10 Hz, (ADCFLT = 0x961F)
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| EVAL-ADUC7060QSPZU1 | 制造商:Analog Devices 功能描述: |
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