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| 型号： | EVAL-ADUC7039QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 46/92页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADUC7039 |
| 设计资源： | ADuC7039QSPZ Gerber Files EVAL-ADuC7039 Schematic & Brd Outline |
| 标准包装： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 类型： | MCU |
| 适用于相关产品： | ADuC7039 |
| 所含物品： | 板 |
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ADuC7039
Data Sheet
Rev. D | Page 50 of 92
The operating mode and clocking mode are controlled using
two MMRs, PLLCON and POWCON, and the status of the
PLL, PLL lock and PLL interrupt, is indicated by PLLSTA.
It is recommended that before powering down the ADuC7039,
switch the clock source for the PLL to the low power oscillator
to reduce wake-up time. The low power oscillator is always
active.
When the ADuC7039 wakes up from power-down, the MCU
core begins executing code as soon as the PLL begins oscillat-
ing. This occurs before the PLL has locked to a frequency of
20.48 MHz. To ensure the Flash/EE memory controller is execut-
ing with a valid clock, the controller is driven with a PLL output
divide-by-eight clock source while the PLL is locking. When
the PLL locks, the PLL output is switched from the PLL output
divide-by-eight to the locked PLL output.
If user code requires an accurate PLL output, user code must
poll the lock bit (PLLSTA[1]) after wake-up before resuming
normal code execution.
The PLL is locked within 2 ms after waking up.
PLLCON is a protected MMR with two 32-bit keys: PLLKEY0
(prewrite key) and PLLKEY1 (postwrite key).
PLLKEY0 = 0x000000AA
PLLKEY1 = 0x00000055
POWCON is a protected MMR with two 32-bit keys:
POWKEY0 (prewrite key) and POWKEY1 (postwrite key).
POWKEY0 = 0x00000001
POWKEY1 = 0x000000F4
Sequence Example
An example of writing to both MMRs is as follows:
For programming the POWCON MMR:
//Function Prototype
Void PowerDown (void)
PowerDown PROC
LDR
r2, = 0x98765432
; Load random number for multiplication
LDR
r3, = 0x12345678
LDR
r0, = 0xffff0400
;Base address
MOVS
r1,#0x1
;POWKEY0 = 1
STR
r1,[r0,#4]
;Set POWKEY0
MOVS
r1,#0x01
;Set POWCON value to recommended value of 0x01 to ensure a
10 MHz core clock
STR
r1,[r0,#8]
MOVS
r1,#0xf4
STR
r1,[r0,#0xc]
;Set POWKEY1
UMLAL
r1,r3,r2,r0
;longest possible assembly multiplication instruction
BX
lr
;Flush ARM7 pipeline
ENDP
For programming the PLLCON MMR:
PLLKEY0
=
0xAA
//PLLCON key
PLLCON
=
0x1
//Switch to precision oscillator.
PLLKEY1
=
0x55
//PLLCON key
iA1*iA2
//PSEUDOCODE-dummy cycle to prevent Flash/EE access during clock
change
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| EVAL-ADUC7060QSPZU1 | 制造商:Analog Devices 功能描述: |
| EVALADUC7060QSPZU2 | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Boxed Product (Development Kits) |
| EVAL-ADUC7061MKZ | 功能描述:开发板和工具包 - ARM Quick Start Development System RoHS:否 制造商:Arduino 产品:Development Boards 工具用于评估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口类型:DAC, ICSP, JTAG, UART, USB 工作电源电压:3.3 V |
| EVAL-ADUC7061MKZ | 制造商:Analog Devices 功能描述:ADUC7061MKZ EvaluationBoard |
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