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| 型号： | EVAL-ADUC7060QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/100页 |
| 文件大小： | 0K |
| 描述： | KIT DEV QUICK START ADUC7060 |
| 产品变化通告： | ADuC7060/1 Idd Specification Change 01/Feb/2010 |
| 设计资源： | ADUC7060 Gerber Files EVAL-ADuC7060 schematic |
| 标准包装： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 类型： | MCU |
| 适用于相关产品： | ADuC7060 |
| 所含物品： | 评估板、电源、缆线、软件、仿真器和说明文档 |
| 其它名称： | Q5189809 |
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ADuC7060
The stack pointer contains the current location of the stack.
Generally, on an ARM7TDMI, the stack starts at the top of the
available RAM area and descends using the area as required. A
separate stack is defined for each of the exceptions. The size of
each stack is user configurable and is dependent on the target
application. When programming using high level languages,
such as C, it is necessary to ensure that the stack does not overflow.
This is dependent on the performance of the compiler that is used.
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (R13) and the link register (R14) as represented
in Figure 8. The FIQ mode has more registers (R8 to R12)
supporting faster interrupt processing. With the increased
number of noncritical registers, the interrupt can be processed
without the need to save or restore these registers, thereby
reducing the response time of the interrupt handling process.
More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in ARM7TDMI
technical and ARM architecture manuals available directly from
ARM Ltd.
higher priority, which can delay entry into the IRQ handling
routine for an arbitrary length of time. This time can be reduced
to 42 cycles if the LDM command is not used; some compilers
have an option to compile without using this command. Another
option is to run the part in Thumb mode where this is reduced
to 22 cycles.
The minimum latency for FIQ or IRQ interrupts is five cycles.
This consists of the shortest time the request can take through
the synchronizer plus the time to enter the exception mode.
Note that the ARM7TDMI initially (first instruction) runs in
ARM (32-bit) mode when an exception occurs. The user can
immediately switch from ARM mode to Thumb mode if required,
for example, when executing interrupt service routines.
MEMORY ORGANIZATION
The ARM7, a von Neumann architecture MCU core sees
memory as a linear array of 232-byte locations. As shown in
namely: a memory area that can be remapped, an SRAM area, a
Flash/EE area, and a memory mapped register (MMR) area.
The first 30 kB of this memory space is used as an area into
which the on-chip Flash/EE or SRAM can be remapped. Any
R0
R1
R2
R3
R4
R5
USABLE IN USER MODE
SYSTEM MODES ONLY
access, either reading or writing, to an area not defined in the
memory map results in a data abort exception.
Memory Format
The ADuC7060 memory organization is configured in little
R6
R7
R8
R9
R10
R11
R12
R13
R14
R8_FIQ
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R13_SVC
R14_SVC
R13_ABT
R14_ABT
R13_IRQ
R14_IRQ
R13_UND
R14_UND
endian format: the least significant byte is located in the lowest
byte address and the most significant byte in the highest byte
address. See Figure 10 for details.
0xFFFFFFFF
MMRs
0xFFFF0000
RESERVED
R15 (PC)
0x00087FFF
FLASH/EE
CPSR
SPSR_FIQ
SPSR_SVC
SPSR_ABT
SPSR_IRQ
SPSR_UND
0x00080000
RESERVED
USER MODE
FIQ SVC ABORT
MODE MODE MODE
Figure 8. Register Organization
IRQ
MODE
UNDEFINED
MODE
0x00040FFF
0x00040000
SRAM
RESERVED
INTERRUPT LATENCY
The worst-case latency for an FIQ consists of the longest time
0x00007FFF
0x00000000
REMAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)
the request can take to pass through the synchronizer, plus the
Figure 9. Memory Map
time for the longest instruction to complete (the longest instruc-
BIT 31
BIT 0
tion is an LDM) that loads all the registers including the PC, plus
the time for the data abort entry, plus the time for FIQ entry. At
the end of this time, the ARM7TDMI is executing the instruc-
tion at 0x1C (FIQ interrupt vector address). The maximum total
BYTE 3
.
.
.
B
7
BYTE 2
.
.
.
A
6
BYTE 1
.
.
.
9
5
BYTE 0
.
.
.
8
4
0xFFFFFFFF
0x00000004
time is 50 processor cycles, or just over 4.88 μs in a system using
a continuous 10.24 MHz processor clock. The maximum IRQ
latency calculation is similar but must allow for the FIQ having
Rev. 0 | Page 19 of 100
3
2 1 0 0x00000000
32 BITS
Figure 10. Little Endian Format
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EVAL-ADUC7060QSPZU1 | 制造商:Analog Devices 功能描述: |
| EVALADUC7060QSPZU2 | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Boxed Product (Development Kits) |
| EVAL-ADUC7061MKZ | 功能描述:开发板和工具包 - ARM Quick Start Development System RoHS:否 制造商:Arduino 产品:Development Boards 工具用于评估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口类型:DAC, ICSP, JTAG, UART, USB 工作电源电压:3.3 V |
| EVAL-ADUC7061MKZ | 制造商:Analog Devices 功能描述:ADUC7061MKZ EvaluationBoard |
| EVAL-ADUC7061MKZU2 | 制造商:Analog Devices 功能描述:PN may be NE CE 制造商:Analog Devices 功能描述:EVALUATION CONTROL BOARD - Boxed Product (Development Kits) |
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