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| 型号： | EVAL-ADUC7060QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 71/100页 |
| 文件大小： | 0K |
| 描述： | KIT DEV QUICK START ADUC7060 |
| 产品变化通告： | ADuC7060/1 Idd Specification Change 01/Feb/2010 |
| 设计资源： | ADUC7060 Gerber Files EVAL-ADuC7060 schematic |
| 标准包装： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 类型： | MCU |
| 适用于相关产品： | ADuC7060 |
| 所含物品： | 评估板、电源、缆线、软件、仿真器和说明文档 |
| 其它名称： | Q5189809 |
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ADuC7060
Table 82. PWMCON MMR Bit Designations
Bit
14
13
12
11
10
9
8:6
5
4
3
2
1
0
Name
Sync
PWM5INV
PWM3NV
PWM1INV
PWMTRIP
ENA
PWMCP[2:0]
POINV
HOFF
LCOMP
DIR
HMODE
PWMEN
Description
Enables PWM synchronization.
Set to 1 by user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low
transition on the P1.2/SYNC pin.
Cleared by user to ignore transitions on the P1.2/SYNC pin.
Set to 1 by user to invert PWM5.
Cleared by user to use PWM5 in normal mode.
Set to 1 by user to invert PWM3.
Cleared by user to use PWM3 in normal mode.
Set to 1 by user to invert PWM1.
Cleared by user to use PWM1 in normal mode.
Set to 1 by user to enable PWM trip interrupt. When the PWMTRIP input is low, the PWMEN bit is cleared and an
interrupt is generated.
Cleared by user to disable the PWMTRIP interrupt.
If HOFF = 0 and HMODE = 1. Note that, if not in H-bridge mode, this bit has no effect.
Set to 1 by user to enable PWM outputs.
Cleared by user to disable PWM outputs.
PWM clock prescaler bits. Sets the UCLK divider.
[000] = UCLK/2.
[001] = UCLK/4.
[010] = UCLK/8.
[011] = UCLK/16.
[100] = UCLK/32.
[101] = UCLK/64.
[110] = UCLK/128.
[111] = UCLK/256.
Set to 1 by user to invert all PWM outputs.
Cleared by user to use PWM outputs as normal.
High side off.
Set to 1 by user to force PWM0 and PWM2 outputs high. This also forces PWM1 and PWM3 low.
Cleared by user to use the PWM outputs as normal.
Load compare registers.
Set to 1 by user to load the internal compare registers with the values in PWMxCOMx on the next transition of the
PWM timer from 0x00 to 0x01.
Cleared by user to use the values previously stored in the internal compare registers.
Direction control.
Set to 1 by user to enable PWM0 and PWM1 as the output signals while PWM2 and PWM3 are held low.
Cleared by user to enable PWM2 and PWM3 as the output signals while PWM0 and PWM1 are held low.
Enables H-bridge mode. 1
Set to 1 by user to enable H-bridge mode and Bit 1 to Bit 5 of PWMCON.
Cleared by user to operate the PWMs in standard mode.
Set to 1 by user to enable all PWM outputs.
Cleared by user to disable all PWM outputs.
1
In H-bridge mode, HMODE = 1. See Table 83 to determine the PWM outputs.
Rev. 0 | Page 71 of 100
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| EVAL-ADUC7060QSPZU1 | 制造商:Analog Devices 功能描述: |
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