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| 型号： | EVAL-ADUC7060QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 31/100页 |
| 文件大小： | 0K |
| 描述： | KIT DEV QUICK START ADUC7060 |
| 产品变化通告： | ADuC7060/1 Idd Specification Change 01/Feb/2010 |
| 设计资源： | ADUC7060 Gerber Files EVAL-ADuC7060 schematic |
| 标准包装： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 类型： | MCU |
| 适用于相关产品： | ADuC7060 |
| 所含物品： | 评估板、电源、缆线、软件、仿真器和说明文档 |
| 其它名称： | Q5189809 |
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ADuC7060
Power and Clock Control Registers
Name:
POWCON0
Name:
Address:
Default value:
Access:
Function:
POWKEY1
0xFFFF0404
0xXXXX
Write
When writing to POWCON0, the value of
Address:
Default value:
Access:
Function:
0xFFFF0408
0x7B
Read and write
This register controls the clock divide bits
controlling the CPU clock (HCLK).
0x01 must be written to this register in the
instruction immediately before writing to
POWCON0.
Table 30. POWCON0 MMR Bit Designations
Bit
7
6
5
4
3
2 to 0
Name
Reserved
XPD
PLLPD
PPD
COREPD
CD[2:0]
Description
This bit must always be set to 0.
XTAL power-down.
Cleared by user to power down the external crystal circuitry.
Set by user to enable the external crystal circuitry.
PLL power-down. Timer peripherals power down if driven from the PLL output clock. Timers driven from an active
clock source remain in normal power mode.
This bit is cleared to 0 to power down the PLL. The PLL cannot be powered down if either the core or peripherals are
enabled; Bit 3, Bit 4, and Bit 5 must be cleared simultaneously.
Set by default, and set by hardware on a wake-up event.
Peripherals power-down. The peripherals that are powered down by this bit are as follows:
SRAM, Flash/EE memory and GPIO interfaces, and SPI/I 2 C and UART serial ports.
Cleared to power down the peripherals. The peripherals cannot be powered down if the core is enabled; Bit 3 and
Bit 4 must be cleared simultaneously.
Set by default, and/or by hardware, on a wake-up event. Wake-up timer (Timer1) can remain active.
Core power-down. If user code powers down the MCU, include a dummy MCU cycle after the power-down
command is written to POWCON0.
Cleared to power down the ARM core.
Set by default and set by hardware on a wake-up event.
Core clock depends on CD setting:
[000] = 10.24 MHz
[001] = 5.12 MHz
[010] = 2.56 MHz
[011] = 1.28 MHz [default value]
[100] = 640 kHz
[101] = 320 kHz
[110] = 160 kHz
[111] = 80 kHz
Table 31. ADuC7060 Power Saving Modes
POWCON0[6:3]
1111
1110
1100
Mode
Active
Pause
Nap
Core
Yes
Peripherals
Yes
Yes
PLL
Yes
Yes
Yes
XTAL/T2/T3
Yes
Yes
Yes
IRQ0 to IRQ3
Yes
Yes
Yes
Start-Up/Power-On Time
130 ms at CD = 0
4.8 μs at CD = 0; 660 μs at CD = 7
4.8 μs at CD = 0; 660 μs at CD = 7
1000
0000
Sleep
Stop
Yes
Yes
Yes
66 μs at CD = 0; 900 μs at CD = 7
66 μs at CD = 0; 900 μs at CD = 7
Rev. 0 | Page 31 of 100
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| EVAL-ADUC7060QSPZU1 | 制造商:Analog Devices 功能描述: |
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