参数资料
型号: EVAL-ADUC7060QSPZ
厂商: Analog Devices Inc
文件页数: 67/100页
文件大小: 0K
描述: KIT DEV QUICK START ADUC7060
产品变化通告: ADuC7060/1 Idd Specification Change 01/Feb/2010
设计资源: ADUC7060 Gerber Files
EVAL-ADuC7060 schematic
标准包装: 1
系列: QuickStart™ PLUS 套件
类型: MCU
适用于相关产品: ADuC7060
所含物品: 评估板、电源、缆线、软件、仿真器和说明文档
其它名称: Q5189809
ADuC7060
Timer2 Control Register
Name:
Address:
Default value:
Access:
Function:
T2CON
0xFFFF0368
0x0000
Read and write
The 16-bit MMR configures the mode of operation of Timer2, as described in detail in Table 79.
Table 79. T2CON MMR Bit Designations
Bit
15:9
8
7
6
5
4
3:2
1
0
Name
T2DIR
T2EN
T2MOD
WDOGMDEN
T2SCALE
WDOGENI
T2PDOFF
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Count up/count down enable.
Set by user code to configure Timer2 to count up.
Cleared by user code to configure Timer2 to count down.
Timer2 enable.
Set by user code to enable Timer2.
Cleared by user code to disable Timer2.
Timer2 operating mode.
Set by user code to configure Timer2 to operate in periodic mode.
Cleared by user to configure Timer2 to operate in free running mode.
Watchdog timer mode enable.
Set by user code to enable watchdog mode.
Cleared by user code to disable watchdog mode.
Reserved. This bit is reserved and should be written as 0 by user code.
Timer2 clock (32.768 kHz) prescaler.
00 = 32.768 kHz (default).
01 = source clock/16.
10 = source clock/256.
11 = reserved.
Watchdog timer IRQ enable.
Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0.
Cleared by user code to disable the IRQ option.
Stop Timer2 when power-down is enabled.
Set by user code to stop Timer2 when the peripherals are powered down using Bit 4 in the POWCON0 MMR.
Cleared by user code to enable Timer2 when the peripherals are powered down using Bit 4 in the
POWCON0 MMR.
Rev. 0 | Page 67 of 100
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