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| 型号： | EVAL-ADUC7060QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 92/100页 |
| 文件大小： | 0K |
| 描述： | KIT DEV QUICK START ADUC7060 |
| 产品变化通告： | ADuC7060/1 Idd Specification Change 01/Feb/2010 |
| 设计资源： | ADUC7060 Gerber Files EVAL-ADuC7060 schematic |
| 标准包装： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 类型： | MCU |
| 适用于相关产品： | ADuC7060 |
| 所含物品： | 评估板、电源、缆线、软件、仿真器和说明文档 |
| 其它名称： | Q5189809 |
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ADuC7060
SPI REGISTERS
The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
SPI Status Register
SPISTA Register
Name:
Address:
Default value:
Access:
Function:
SPISTA
0xFFFF0A00
0x00000000
Read only
This 32-bit MMR contains the status of the SPI interface in both master and slave modes.
Table 104. SPISTA MMR Bit Designations
Bit
15:12
11
10:8
7
6
5
4
3:1
0
Name
SPIREX
SPIRXFSTA[2:0]
SPIFOF
SPIRXIRQ
SPITXIRQ
SPITXUF
SPITXFSTA[2:0]
SPIISTA
Description
Reserved bits.
SPI receive FIFO excess bytes present. This bit is set when there are more bytes in the receive FIFO than
indicated in the SPIRXMDE bits in SPICON.
This bit is cleared when the number of bytes in the FIFO is equal to or less than the number in SPIRXMDE.
SPI receive FIFO status bits.
[000] = receive FIFO is empty.
[001] = 1 valid byte in the FIFO.
[010] = 2 valid byte in the FIFO.
[011] = 3 valid byte in the FIFO.
[100] = 4 valid byte in the FIFO.
SPI receive FIFO overflow status bit.
Set when the receive FIFO was already full when new data was loaded to the FIFO. This bit generates an
interrupt except when SPIRFLH is set in SPICON.
Cleared when the SPISTA register is read.
SPI receive IRQ status bit.
Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required
number of bytes have been received.
Cleared when the SPISTA register is read.
SPI transmit IRQ status bit.
Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number
of bytes have been transmitted.
Cleared when the SPISTA register is read.
SPI transmit FIFO underflow.
This bit is set when a transmit is initiated without any valid data in the transmit FIFO. This bit generates an
interrupt except when SPITFLH is set in SPICON.
Cleared when the SPISTA register is read.
SPI transmit FIFO status bits.
[000] = transmit FIFO is empty.
[001] = 1 valid byte in the FIFO.
[010] = 2 valid byte in the FIFO.
[011] = 3 valid byte in the FIFO.
[100] = 4 valid byte in the FIFO.
SPI interrupt status bit.
Set to 1 when an SPI based interrupt occurs.
Cleared after reading SPISTA.
Rev. 0 | Page 92 of 100
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相关代理商/技术参数 |
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| EVAL-ADUC7060QSPZU1 | 制造商:Analog Devices 功能描述: |
| EVALADUC7060QSPZU2 | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Boxed Product (Development Kits) |
| EVAL-ADUC7061MKZ | 功能描述:开发板和工具包 - ARM Quick Start Development System RoHS:否 制造商:Arduino 产品:Development Boards 工具用于评估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口类型:DAC, ICSP, JTAG, UART, USB 工作电源电压:3.3 V |
| EVAL-ADUC7061MKZ | 制造商:Analog Devices 功能描述:ADUC7061MKZ EvaluationBoard |
| EVAL-ADUC7061MKZU2 | 制造商:Analog Devices 功能描述:PN may be NE CE 制造商:Analog Devices 功能描述:EVALUATION CONTROL BOARD - Boxed Product (Development Kits) |
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