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参数资料
| 型号： | EVAL-ADUC7060QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 42/100页 |
| 文件大小： | 0K |
| 描述： | KIT DEV QUICK START ADUC7060 |
| 产品变化通告： | ADuC7060/1 Idd Specification Change 01/Feb/2010 |
| 设计资源： | ADUC7060 Gerber Files EVAL-ADuC7060 schematic |
| 标准包装： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 类型： | MCU |
| 适用于相关产品： | ADuC7060 |
| 所含物品： | 评估板、电源、缆线、软件、仿真器和说明文档 |
| 其它名称： | Q5189809 |
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ADuC7060
Bit
6:4
3:
1:0
Name
ADC1REF[2:0]
BUF_BYPASS[1:0]
Description
Auxiliary channel ADC reference select.
[000] = internal reference selected. In ADC low power mode, the voltage reference selection is controlled by
ADCMODE[5].
[001] = external reference inputs (VREF+, VREF?) selected. Set the HIGHEXTREF1 bit if reference voltage
exceeds 1.3 V.
[010] = auxiliary external reference inputs (ADC4/EXT_REF2IN+, ADC5/EXT_REF2IN?) selected. Set the
HIGHEXTREF1 bit if reference voltage exceeds 1.35 V.
[011] = (AVDD, AGND) divide-by-two selected. If this configuration is selected, the HIGHEXTREF1 bit is set
automatically.
[100] = (AVDD, ADC3). ADC3 can be used as the negative input terminal for the reference source.
[101] to [111] = reserved.
Buffer bypass.
[00] = full buffer on. Both positive and negative buffer inputs active.
[01] = negative buffer is bypassed, positive buffer is on.
[10] = negative buffer is on, positive buffer is bypassed.
[11] = full buffer bypass. Both positive and negative buffer inputs are off.
Digital gain. Select for auxiliary ADC inputs.
[00] = ADC1 gain = 1.
[01] = ADC1 gain = 2.
[10] = ADC1 gain = 4.
[11] = ADC1 gain = 8.
ADC Filter Register
Name:
Address:
Default value:
Access:
Function:
ADCFLT
0xFFFF0514
0x0007
Read and write
The ADC filter MMR is a 16-bit register that controls the speed and resolution of both the on-chip ADCs. Note that, if
ADCFLT is modified, the primary and auxiliary ADCs are reset.
Table 43. ADCFLT MMR Bit Designations
Bit
15
14
13 to 8
Name
CHOPEN
RAVG2
AF[5:0]
Description
Chop enable. Set by user to enable system chopping of all active ADCs. When this bit is set, the ADC has very low offset
errors and drift, but the ADC output rate is reduced by a factor of three if AF = 0 (see sinc3 decimation factor, Bits[6:0]
in this table). If AF > 0, then the ADC output update rate is the same with chop on or off. When chop is enabled, the
settling time is two output periods.
Running average-by-2 enable bit.
Set by user to enable a running-average-by-2 function, reducing ADC noise. This function is automatically enabled
when chopping is active. It is an optional feature when chopping is inactive, and if enabled (when chopping is
inactive), does not reduce the ADC output rate but does increase the settling time by one conversion period.
Cleared by user to disable the running average function.
Averaging factor (AF). The values written to these bits are used to implement a programmable first-order sinc3 post
filter. The averaging factor can further reduce ADC noise at the expense of output rate as described in Bits[6:0] sinc3
decimation factor in this table.
Rev. 0 | Page 42 of 100
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相关代理商/技术参数 |
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| EVAL-ADUC7060QSPZU1 | 制造商:Analog Devices 功能描述: |
| EVALADUC7060QSPZU2 | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Boxed Product (Development Kits) |
| EVAL-ADUC7061MKZ | 功能描述:开发板和工具包 - ARM Quick Start Development System RoHS:否 制造商:Arduino 产品:Development Boards 工具用于评估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口类型:DAC, ICSP, JTAG, UART, USB 工作电源电压:3.3 V |
| EVAL-ADUC7061MKZ | 制造商:Analog Devices 功能描述:ADUC7061MKZ EvaluationBoard |
| EVAL-ADUC7061MKZU2 | 制造商:Analog Devices 功能描述:PN may be NE CE 制造商:Analog Devices 功能描述:EVALUATION CONTROL BOARD - Boxed Product (Development Kits) |
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