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| 型号： | EVAL-ADUC7060QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 40/100页 |
| 文件大小： | 0K |
| 描述： | KIT DEV QUICK START ADUC7060 |
| 产品变化通告： | ADuC7060/1 Idd Specification Change 01/Feb/2010 |
| 设计资源： | ADUC7060 Gerber Files EVAL-ADuC7060 schematic |
| 标准包装： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 类型： | MCU |
| 适用于相关产品： | ADuC7060 |
| 所含物品： | 评估板、电源、缆线、软件、仿真器和说明文档 |
| 其它名称： | Q5189809 |
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ADuC7060
Table 41. ADC0CON MMR Bit Designations
Bit
15
14:13
12
11
10
9:6
5:4
3:0
Name
ADC0EN
ADC0DIAG[1:0]
HIGHEXTREF0
AMP_CM
ADC0CODE
ADC0CH[3:0]
ADC0REF[1:0]
ADC0PGA[3:0].
Description
Primary channel ADC enable.
This bit is set to 1 by user code to enable the primary ADC.
Clearing this bit to 0 powers down the primary ADC and resets the respective ADC ready bit in the ADCSTA MMR
to 0.
Diagnostic current source enable bits.
0, 0 = current sources off.
0, 1 = enables a 50 μA current source on selected positive input (for example, ADC0).
1, 0 = enables a 50 μA current source on selected negative input (for example, ADC1).
1, 1 = enables a 50 μA current source on both selected inputs (for example, ADC0 and ADC1).
This bit must be set high if the external reference for ADC0 exceeds 1.35 V.
Clear this bit when using the internal reference or an external reference of less than 1.35 V.
This bit is set to 1 by user to set the PGA output common-mode voltage to AVDD/2.
This bit is cleared to 0 by user code to set the PGA output common-mode voltage to the PGA input common-
mode voltage level.
Primary channel ADC output coding.
This bit is set to 1 by user code to configure primary ADC output coding as unipolar.
This bit is cleared to 0 by user code to configure primary ADC output coding as twos complement.
Primary channel ADC input select.
[0000] = ADC0/ADC1 (differential mode).
[0001] = ADC0/ADC5 (single-ended mode).
[0010] = ADC1/ADC5 (single-ended mode).
[0011] = VREF+, VREF?. Note: This is the reference selected by the ADC0REF bits.
[0100] = Not used. This bit combination is reserved for future functionality and should not be written.
[0101] = ADC2/ADC3 (differential mode).
[0110] = ADC2/ADC5 (single-ended mode).
[0111] = ADC3/ADC5 (single-ended mode).
[1000] = internal short to ADC0.
[1001] = internal short to ADC1.
Primary channel ADC reference select.
0, 0 = internal reference selected. In ADC low power mode, the voltage reference selection is controlled by
ADCMODE[5].
0, 1 = external reference inputs (VREF+, VREF?) selected. Set the HIGHEXTREF0 bit if the reference voltage
exceeds 1.3 V.
1, 0 = auxiliary external reference inputs (ADC4/EXT_REF2IN+, ADC5/EXT_REF2IN?) selected. Set the
HIGHEXTREF0 bit if the reference voltage exceeds 1.3 V.
1, 1 = (AVDD, AGND) divide-by-two selected.
Primary channel ADC gain select. Note, nominal primary ADC full-scale input voltage = (VREF/gain).
0, 0, 0, 0 = ADC0 gain of 1. Buffer is active.
0, 0, 0, 1 = ADC0 gain of 2.
0, 0, 1, 0 = ADC0 gain of 4 (default value). Enables the in-amp.
0, 0, 1, 1 = ADC0 gain of 8.
0, 1, 0, 0 = ADC0 gain of 16.
0, 1, 0, 1 = ADC0 gain of 32.
0, 1, 1, 0 = ADC0 gain of 64 (maximum PGIA gain setting).
0, 1, 1, 1 = ADC0 gain of 128 (extra gain implemented digitally).
1, 0, 0, 0 = ADC0 gain of 256.
1, 0, 0, 1 = ADC0 gain of 512.
1, x, x, x = ADC0 gain is undefined.
Rev. 0 | Page 40 of 100
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| EVAL-ADUC7060QSPZU1 | 制造商:Analog Devices 功能描述: |
| EVALADUC7060QSPZU2 | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Boxed Product (Development Kits) |
| EVAL-ADUC7061MKZ | 功能描述:开发板和工具包 - ARM Quick Start Development System RoHS:否 制造商:Arduino 产品:Development Boards 工具用于评估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口类型:DAC, ICSP, JTAG, UART, USB 工作电源电压:3.3 V |
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