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| 型号： | HSP50210JC-52Z |
| 厂商： | Intersil |
| 文件页数： | 15/51页 |
| 文件大小： | 0K |
| 描述： | IC DEMODULATOR COSTAS 84-PLCC |
| 标准包装： | 15 |
| 功能： | 解调器 |
| 频率： | 52MHz |
| RF 型： | AM，FM |
| 封装/外壳： | 84-LCC（J 形引线） |
| 包装： | 管件 |
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HSP50210
AGC GAIN
MANTISSA
1.0 TO 1.9844
(0.0156 STEPS)
EXPONENT
2 0 TO 2 3
INTEGRATE AND
G = 1.0 - 1.9844*2 3
DUMP FILTER
SYNTHESIZER/
RRC
INT/DUMP
INT/DUMP
SAMPLE PAIR
MIXER
FILTER
ACCUMULATOR SHIFTER
SUMMER
8
G = 1.0, 0.5 (NOTE 1) G = 1.0, 1.13 (NOTE 2)
PART
INPUT
G AGC
-2 5
2 4
2 3
L
I
M /
I
T
G = 1 TO 16
-2 4
2 3
G = 2 0 TO 2 -4
-2 4
2 3
L
I
M
I
T
G = 0.5, 1.0 (NOTE 3)
INPUT TO
SOFT DECISION
SLICER
AND
SYMBOL TRACKING
BLOCK
2 2
2 2
2 2
BINARY
POINT
-2 0
2 -1
2 -9
(NOTE 4)
-2 0
2 -1
2 -10
-2 1
2 0
2 -1
2 -10
2 1
2 0
2 -1
2 -9
-2 0
2 -1
2 -7
2 1
2 0
2 -1
2 -7
2 1
2 0
2 -1
2 -11
-2 0
2 -1
2 -6
-2 0
2 -1
2 -6
RND
RND
RND
2 -7
INPUT TO CARTESIAN-TO-POLAR CONVERTER
IF AGC OUTPUT SELECTED INPUT TO CARTESIAN-TO-POLAR CONVERTER
IF INT/DUMP OUTPUT SELECTED
NOTES:
1. If the Mixer is enabled, the result of the complex multiply is scaled by two (G = 0.5). If the mixer is bypassed, the data passes unmodified (G = 1.0).
2. If the Root Raised Cosine Filter is enabled, a gain of G = 1.13 is introduced. If the RRC filters bypassed, the gain is unity.
3. If the integrate and Dump Filter is bypassed the Sample Pair summer has a gain of G = 1.0 and the 2 -7 -bit position is set to 1. If the integrate
and dump is enabled, the sample pair sum is scaled by one half (G = 0.5).
4. The negative sign on the MSBs indicates use of 2’s complement data format.
FIGURE 10. GAIN DISTRIBUTION AND INTERMEDIATE BIT WEIGHTINGS
Gain Distribution
The gain distribution in the DCL is shown in Figure 10.
These gains consist of a combination of fixed,
programmable, and adaptive gains. The fixed gains are
introduced by processing elements such as the Mixer and
Square Root of Root Raised Cosine Filter. The adaptive
gains are set to compensate for variations in input signal
strength.
The main signal path, with processing block gains and path
bit weightings, is shown in Figure 10. The quadrature inputs
to the HSP50210 are 10-bit fractional two’s complement
numbers with relative bit weightings, as shown in Figure 10.
The first element in the processing chain is the Mixer, which
scales the quadrature outputs of the complex multiplier by
1/2 providing a gain of G = 0.5. If the Mixer is bypassed, the
signal is passed unmodified with a gain of 1.0. Following the
mixer, the quadrature signal is passed to the fixed coefficient
RRC filtering block, which has a gain of 1.13 if enabled and
1.0 if bypassed. Next, the AGC supplies gain to maintain an
optimal signal level at the input to the Soft Decision Slicer,
Cartesian-to-Polar Converter, and the Symbol Tracking
Loop. The gain supplied by the AGC ranges from 1.0 to
1.9844*2 3 .
15
Following the AGC, the signal path is limited to 8 bits and
passed through the Integrate and Dump Filter en route to the
Soft Decision Slicer and Symbol Tracking Block. The I and D
Filter uses an accumulator together with a sample pair summer
to achieve the desired decimation rate. The I and D shifter is
provided to compensate for the gain introduced by the I and D
Accumulator. The accumulator introduces gain equal to the
decimation factor R, and the shifter gain can be set to 1/R. For
example, if the I and D Filter decimation of 16 is chosen, the I
and D Accumulator will accumulate 8 samples before dumping,
which produces a gain of 8. Thus, for unity gain, the I and D
Shifter would be set for a gain of 2 -3 . The Sample Pair Summer
is unity gain since its output is scaled by one-half.
Symbol Tracking
The symbol tracking loop adjusts the baseband sampling
frequency to force sampling of the baseband waveform at
optimal points for data decisions. The key elements of this loop
are the Sampling Error Detector and Symbol Tracking Loop
Filter shown in Figure 11. The output of these two blocks is a
frequency correction term which is used to adjust the baseband
sample frequency external to the HSP50210. In typical
applications, the frequency correction term is fed back to the
HSP50110 to adjust baseband sampling via the Resampling
NCO (see HSP50110 Datasheet).
FN3652.5
July 2, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HSP50210JI-52 | 功能描述:上下转换器 COSTAS DEMODULATOR,84 PLCC,52MHZ,IND RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| HSP50210JI-52Z | 功能描述:上下转换器 COSTAS DEMODULATOR 84 PLCC 52MHZ IND RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| HSP50214 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214AVC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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