参数资料
型号: HSP50210JC-52Z
厂商: Intersil
文件页数: 42/51页
文件大小: 0K
描述: IC DEMODULATOR COSTAS 84-PLCC
标准包装: 15
功能: 解调器
频率: 52MHz
RF 型: AM,FM
封装/外壳: 84-LCC(J 形引线)
包装: 管件
HSP50210
TABLE 39. HALT LOCK DETECTOR FOR READING CONTROL REGISTER
DESTINATION ADDRESS = 24
BIT
POSITION
N/A
FUNCTION
Stop Lock Detector for
Reading
DESCRIPTION
Writing this location halts the Lock Detector State Machine at the end of the current Lock Detector
Accumulator integration cycle. This function is provided so that the Lock Detector integrators can be
stopped for reading via the microprocessor interface (only useful when the Lock Detector is under
internal state machine control). Bit 7 of the internal status register can be monitored via the
Microprocessor Interface to determine when the Lock Detector has stopped and is ready for reading.
See Table 14 for information on the internal status bits. The Lock Detector will remain stopped until
restarted (see Restart Lock Detector Control Register: Table 40).
TABLE 40. RESTART LOCK DETECTOR CONTROL REGISTER
DESTINATION ADDRESS = 25
BIT
POSITION
N/A
FUNCTION
Restart Lock Detector
DESCRIPTION
Writing this location restarts the Lock Detector State Machine following a read of the Lock Detector. Note:
Stopping the Lock Detector for reading is not required in Microprocessor Control Mode since the Lock
Detector Accumulators stop at the end of each integration cycle. See also Table 45.
TABLE 41. SOFT DECISION SLICER CONFIGURATION CONTROL REGISTER
DESTINATION ADDRESS = 26
BIT
POSITION
31-8
7
6-0
FUNCTION
Not Used
Slicer Output Format
Soft Decision
Threshold
DESCRIPTION
No programming required.
0 = Soft decision outputs are in sign/magnitude format.
1 = Soft decision outputs are in two’s complement format.
The input to the slicer is compared against thresholds which are 1x, 2x and 3x the value programmed
here. The slicer output depends on the relationship of the I or Q magnitude to the 3 soft thresholds as
given in Table 9. The threshold is programmed as a fractional unsigned value with the following bit
weightings:
0. 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 .
Note: Since the signal magnitude on either the I or Q path ranges between 0.0 and ~ 1.0, the threshold
value should not exceed 1.0/3 = 0.33. Bit position 6 is the MSB.
TABLE 42. SERIAL OUTPUT CONFIGURATION CONTROL REGISTER
DESTINATION ADDRESS = 27
BIT
POSITION
31-16
15-13
12
11
FUNCTION
Not Used
Reserved
Serial Data Sync
Polarity
(SOF output)
Serial Data Sync
Polarity
(COF output)
42
DESCRIPTION
No programming required.
Set to zero for proper operation.
0 = SOFSYNC pulses “High” one serial clock before data word on SOF.
1 = SOFSYNC pulses “Low” one serial clock before data word on SOF.
Set to 0 for use with the HSP50110.
0 = COFSYNC pulses “High” one serial clock before data word on COF.
1 = COFSYNC pulses “Low” one serial clock before data word on COF.
Set to 0 for use with the HSP50110.
FN3652.5
July 2, 2008
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