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参数资料
| 型号： | HSP50210JC-52Z |
| 厂商： | Intersil |
| 文件页数： | 18/51页 |
| 文件大小： | 0K |
| 描述： | IC DEMODULATOR COSTAS 84-PLCC |
| 标准包装： | 15 |
| 功能： | 解调器 |
| 频率： | 52MHz |
| RF 型： | AM，FM |
| 封装/外壳： | 84-LCC（J 形引线） |
| 包装： | 管件 |
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HSP50210
HARD DECISION
THRESHOLD
TABLE 7. SLICER INPUT TO OUTPUT MAPPING
SLICER INPUT MAGNITUDE
‘1’ DECISION
‘1’
‘0’ DECISION
‘0’
RELATIVE TO
STRONGER
WEAKER
WEAKER
STRONGER
PROBABILITY
DENSITY
FUNCTION
+
>
>
>
011
011
-0.5
0.0
0.5
+
>
>
≤
010
010
+
+
>
≤
≤
<
<
<
001
000
001
000
FS
-
≤
<
<
100
111
1/2
1/3
MSB
MSB-1
MSB-1
THRESHOLD
-
-
>
>
≤
>
<
≤
101
110
110
101
0
1/3
1/2
MSB
MSB-1
MSB-1
THRESHOLD
- > > >
Carrier Phase Error Detector
111
100
-FS
FIGURE 13. OVERLAY OF THE HARD/SOFT DECISION
THRESHOLDS ON THE SYMBOL PROBABILITY
DENSITY FUNCTIONS (PDFs) FOR BPSK/QPSK
SIGNALS)
The soft decision threshold represents a range of
magnitude values from 0.0 to ~ 0.5. Note: Since the input to
the slicer has a range of 0.0 to ~ 1.0, the threshold setting
should be set to less than 1.0/3 = 0.33. This avoids
saturation. The slicer decisions are output in either a two’s
complement or sign/magnitude format (see Soft Decision
Slicer Configuration Control Register, Bit 7: Table 41 on
page 42). The slicer input to output mapping for a range of
input magnitudes is given in Table 7. For example, a
negative input to the slicer whose magnitude is greater
than twice the programmable threshold but less than 3x the
threshold would produce a sign/magnitude output of 110
(BINARY). The I and Q inputs to the slicer are encoded into
3-bit soft decisions ISOFT(2-0) and QSOFT(3-0). These
signals are routed to the OUTA(9-4) outputs by the Output
Configuration Control Register Selector bits 0-3 (see
Table 43 on page 44).
18
The Carrier Phase Error is computed by removing the
phase modulation from the phase output of the
Cartesian-to-Polar Converter. To remove the modulation,
the phase term is rotated and multiplied (modulo 2 π ) to fold
the Phase Error into an arc centered about 0° but
encompasses the whole plane, as shown in Figure 14. The
phase rotation is performed by adding a 4-bit two’s
complement phase offset (resolution 22.5°) to the 4 MSBs
of the 8-bit phase term. The multiplication is performed by
left shifting the result from 0 to 3 positions with the MSBs
discarded and zeros inserted into the LSBs. For example,
Carrier Phase Error produces I/Q constellation points which
are rotated from the expected constellation points as
shown in Figure 14. By adding an offset of 45° (0010 0000
binary) and multiplying by 4 (left shift by two positions) the
phase modulation is removed, and the error is folded into a
90° arc centered at 0°. The left axis represents a decision
boundary of ±45°C, implying the vertical axis is ±22.5° as
shown in Figure 15. The phase offset and shift factors
required for different PSK orders is given in Table 9 on
page 21. Configuration of the Carrier Phase Error Detector
is done via the Carrier Phase Error Detector Control
Register, bits 0 to 5, (see Table 18 on page 33). The Phase
Error term may be selected for output via the Output
Selector Configuration Control Register, bits 0 to 3 (see
Table 43 on page 44).
FN3652.5
July 2, 2008
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相关代理商/技术参数 |
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|---|---|
| HSP50210JI-52 | 功能描述:上下转换器 COSTAS DEMODULATOR,84 PLCC,52MHZ,IND RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| HSP50210JI-52Z | 功能描述:上下转换器 COSTAS DEMODULATOR 84 PLCC 52MHZ IND RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| HSP50214 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214AVC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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