参数资料
型号: HSP50210JC-52Z
厂商: Intersil
文件页数: 29/51页
文件大小: 0K
描述: IC DEMODULATOR COSTAS 84-PLCC
标准包装: 15
功能: 解调器
频率: 52MHz
RF 型: AM,FM
封装/外壳: 84-LCC(J 形引线)
包装: 管件
HSP50210
WR
RD
DON’T CARE
A0-2
0
1
2
3
4
0
1
C0-7
CLK
1
2
3
4
EARLIEST TIME ANOTHER
LOAD CAN BEGIN
NOTE: These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify
that the processor waveforms meet the parameters in “Waveforms” on page 50 to ensure proper operation. The Processor waveforms are not
required to be synchronous to CLK. They are shown that way to clarify the illustration.
FIGURE 21. CONTROL REGISTER LOADING SEQUENCE
WR
RD
DON’T CARE
ADDRESS IS ASYNCHRONOUS TO CLK
A0-2
4
5
3
2
1
0
C0-7
CLK
29
1
2
3
0
4
5
6
MSB
LSB
DATA IS
ASYNCHRONOUS
TO CLK
1
2
3 4
5
LOAD OUTPUT ENABLE
HOLDING REG HOLDING
REG
FOR
READ
WAIT
6 CLKs
DELAY
TO
RD
ASSERT
READ
READ
READ
READ
NOTE: These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify
that the processor waveforms meet the parameters in “Waveforms” on page 50 to ensure proper operation. The Processor waveforms are not
required to be synchronous to CLK. They are shown that way to clarify the illustration.
1. Load the Write Address Register with 29 dec to load the output holding registers.
2. Enable Carrier Loop Filter Lag Accumulator holding register for reading.
3. Select the MSByte of the output holding register for output.
4. Assert RD low to output data on C0-7. (Must wait for 6 CLKs after loading the holding registers).
5. Select other bytes of holding register by changing A0-2 and asserting RD.
FIGURE 22. LOOP FILTER ACCUMULATOR READ SEQUENCE
29
FN3652.5
July 2, 2008
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