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参数资料
| 型号： | HSP50210JC-52Z |
| 厂商： | Intersil |
| 文件页数： | 25/51页 |
| 文件大小： | 0K |
| 描述： | IC DEMODULATOR COSTAS 84-PLCC |
| 标准包装： | 15 |
| 功能： | 解调器 |
| 频率： | 52MHz |
| RF 型： | AM，FM |
| 封装/外壳： | 84-LCC（J 形引线） |
| 包装： | 管件 |
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HSP50210
Search. The frequency uncertainty is swept by enabling the
Frequency Sweep Block to the lag path of the Carrier
Tracking Loop Filter. The acquisition parameters are
enabled to the Loop Filters and the Lock Detector
Accumulators. Phase lock is obtained when the Lock
Counter rolls over before the Phase Error Accumulator
(average Phase Error is less than the lock threshold).
Verify. Once phase lock is obtained, the frequency sweep is
disabled and the tracking parameters are enabled. Lock is
verified if the accumulated Phase Error is below the
threshold for a programmable number of Integration Periods.
False lock conditions are also monitored by comparing the
roll over of the False Lock Accumulator to that of the
Integration Counter. If the False Lock Accumulator rolls over
before the Integration Counter, a false lock condition exists.
False Lock. Once a false lock has been determined, the
Frequency Sweep block is enabled to move the carrier
tracking beyond the false lock region. The Frequency Sweep
is performed for a programmable number of Integration
Periods before returning to the search state.
Lock. When phase lock has been verified, the Lock status
output is asserted and the False Lock Detector is disabled.
The lock state is maintained as long as the Integration
Counter rolls over before the Phase Error Accumulator.
If the acquisition and tracking process is controlled externally,
the Phase Error Accumulator and False Lock Accumulators
are monitored by an external processor to determine when
lock has been achieved. In this mode the accumulator
pre-loads are typically set to zero and the accumulator output
is compared in the processor against a threshold equal to the
maximum Phase Error per sample times the number of
samples per Integration Period. The accumulators stop after
each Integration Period to hold their outputs for reading via
the Microprocessor Interface (see Read Enable Address Map;
Table 13 on page 28). The accumulators are restarted by
writing the Initialize Lock Detector Control address (see
Initialize Lock Detector Control Register: Table 45 on
page 46). To simplify the processor interface, the LKINT
output is provided to interrupt the processor when the
accumulator integration period is complete. The processor
controls the use of the acquisition/tracking parameters and
lock status line by setting the appropriate bits in the
Acquisition/Tracking Configuration Control Register (see
Table 38 on page 41). In addition, the frequency sweep
function is enabled via the Microprocessor Interface.
PHASE
PHASE
FALSE
FALSE
DWELL
INT
INT
ERROR
ERROR
LOCK
LOCK
COUNT
“0”
PERIOD
PERIOD
PRELOAD PRELOAD
PRELOAD PRELOAD
ACQ
TRACK
ACQ
TRACK
ACQ
TRACK
ACQ
TRACK
GAIN
FALSE LOCK/
ERROR
PHASE
ERROR
FREQUENCY
ERROR
MUX
MUX
MUX
MUX
“0”
|X|
|X|
|X|
DWELL
COUNTER
TC
INTEGRATION
COUNTER
START
TC
+
REG
+
REG
+
REG
SWEPT
25
OVERFLOW
LOCK DETECTOR STATE MACHINE
ACQUIRE/
TRACK
FIGURE 17. LOCK DETECTOR BLOCK DIAGRAM
OVERFLOW
FN3652.5
July 2, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HSP50210JI-52 | 功能描述:上下转换器 COSTAS DEMODULATOR,84 PLCC,52MHZ,IND RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| HSP50210JI-52Z | 功能描述:上下转换器 COSTAS DEMODULATOR 84 PLCC 52MHZ IND RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| HSP50214 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214AVC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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