参数资料
型号: HY27SS16561M-FCP
厂商: HYNIX SEMICONDUCTOR INC
元件分类: PROM
英文描述: 16M X 16 FLASH 1.8V PROM, 10000 ns, PBGA63
封装: 9 X 11 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, FBGA-63
文件页数: 22/44页
文件大小: 644K
代理商: HY27SS16561M-FCP
Rev 0.4 / Jun. 2004
29
Preliminary
HY27SS(08/16)561M Series
HY27US(08/16)561M Series
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
Table 15: AC Characteristics for Operation (3.3V Device and 1.8V Device)
Alt.
Sym-
bol
Sym-
bol
Parameter
3.3V
Device
1.8V
Device
Unit
tALLRL1
tAR1
Address Latch Low to Read En-
able Low
Read Electronic Signature
Min
10
ns
tALLRL2
tAR2
Read cycle
Min
50
ns
tBHRL
tRR
Ready/Busy High to Read Enable Low
Min
20
ns
tBLBH1
tR
Ready/Busy Low to Ready/
Busy High
Read Busy time, 128Mb,
256Mb
Max
10
us
tBLBH2
tPROG
Program Busy time
Max
500
us
tBLBH3
tBERS
Erase Busy time
Max
3
ms
tBLBH4
tRST
Reset Busy time, during
ready
Max
5
us
Reset Busy time, during read
Max
5
us
Reset Busy time, during pro-
gram
Max
10
us
Reset Busy time, during
erase
Max
500
us
tCLLRL
tCLR
Command Latch Low to Read Enable Low
Min
10
ns
tDZRL
tIR
Data Hi-Z to Read Enable Low
Min
0
ns
tEHBH
tCRY
Chip Enable High to Ready/Busy High (CE intercepted read)
Max
60+tr(1)
ns
tEHEL
tCEH
Chip Enable High to Chip Enable Low(2)
Min
100
ns
tEHQZ
tCHZ
Chip Enable High to Output Hi-Z
Max
20
ns
tELQV
tCEA
Chip Enable Low to Output Valid
Max
45
ns
tRHBL
tRB
Read Enable High to Ready/Busy
Low
Max
100
ns
tRHRL
tREH
Read Enable High to Read
Enable Low
Read Enable High Hold time
Min
15
ns
tRHQZ
tRHZ
Read Enable High to Output Hi-Z
Min
15
ns
Max
30
tRLRH
tRP
Read Enable Low to Read Enable
High
Read Enable Pulse Width
Min
30
ns
tRLRL
tRC
Read Enable Low to Read Enable
Low
Read Cycle time
Min
50
60
ns
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