35
8393B-MCU Wireless-02/13
ATmega256/128/64RFR2
That means if the controller runs with about 16MHz or faster, at least three wait cycles
are generated, but if the controller runs with about 4MHz, no wait cycles are inserted. A
register access is only possible, if the transceiver clock is available. Otherwise it returns
0x00 regardless of the current register content. Therefore the transceiver must be
enabled (PRR1 Register) and not in SLEEP state.
9.3.1.2 Frame Buffer Access
The 128-byte Frame Buffer can hold the PHY service data unit (PSDU) data of one
IEEE 802.15.4 compliant RX or one TX frame of maximum length at a time. A detailed
introduction to the IEEE 802.15.4 frame format can be found in section
"Introduction –The Frame Buffer is located within the controller I/O address space above of the
transceiver register set. The first byte of the Frame Buffer can be accessed with the
symbolical address TRXFBST and the last byte can be accessed with the symbolical
address TRXFBEND. Random access to single frame bytes is possible with “TRXFBST
+ byte index” or “TRXFBEND – byte index”. In contrast to the transceiver register
access, the Frame Buffer allows single cycle read/write operations for all controller
clock speeds.
The content of the Frame Buffer is only overwritten by a new received frame or a Frame
Buffer write access.
The Frame Buffer usage is different between received and transmitted frames.
Therefore it is not possible to retransmit a received frame without modifying the frame
buffer.
On received frames, the frame length byte is not stored in the Frame Buffer, but can be
accessed over the TST_FRAME_LENGTH register. During frame receive, the Link
appended to the frame data in the Frame Buffer.
For frame transmission, the first byte of the Frame Buffer must contain the frame length
information followed by the frame data. The TST_FRAME_LENGTH register does not
need to be written in this case.
A detailed description of the Frame Buffer usage for receive and transmit frames can be
Notes:
1. The Frame Buffer is shared between RX and TX; therefore, the frame data are overwritten by
new incoming frames. If the TX frame data are to be retransmitted, it must be ensured that no
frame was received in the meanwhile.
2. To avoid overwriting during receive, Dynamic Frame Buffer Protection can be enabled. For
3. It is not possible to retransmit received frames without inserting the frame length information at
the beginning of the Frame Buffer. That requires a complete read out of the received frame
and rewriting the modified frame to the Frame Buffer.
4. For exceptions, e.g. receiving acknowledgement frames in Extended Operating Mode
9.3.1.3 Transceiver Pin Register TRXPR
The Transceiver Pin Register TRXPR is located in the Controller clock domain and is
accessible even if the transceiver is in sleep state. This register provides access to the